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FDML7610S PowerTrench Power Stage April 2013 FDML7610S PowerTrench Power Stage Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally Max r = 7.5 m at V = 10 V, I = 12 A DS(on) GS D connected to enable easy placement and routing of synchronous Max r = 12 m at V = 4.5 V, I = 10 A DS(on) GS D buck converters. The control MOSFET (Q1) and synchronous Q2: N-Channel TM SyncFET (Q2) have been designed to provide optimal power Max r = 4.2 m at V = 10 V, I = 17 A DS(on) GS D efficiency. Max r = 5.5 m at V = 4.5 V, I = 14 A DS(on) GS D Applications RoHS Compliant Computing Communications General Purpose Point of Load Notebook V CORE D1 D1 D1 Pin 1 G1 Q 2 D1 S2 D1 5 4 PHASE PHASE D1 S2 6 3 (S1/D2) D1 S2 7 2 S2 S2 G2 S2 G1 8 1 G2 Q 1 Top Bottom MLP 3X4.5 MOSFET Maximum Ratings T = 25 C unless otherwise noted A Symbol Parameter Q1 Q2 Units V Drain to Source Voltage 30 30 V DS V Gate to Source Voltage (Note 3) 20 20 V GS Drain Current -Continuous (Package limited) T = 25 C 30 28 C -Continuous (Silicon limited) T = 25 C 40 60 C I A D 1a 1b -Continuous T = 25 C 12 17 A -Pulsed 40 40 1a 1b Power Dissipation for Single Operation T = 25 C 2.1 2.2 A P W D 1c 1d T = 25 C 0.8 0.9 A T , T Operating and Storage Junction Temperature Range -55 to +150 C J STG Thermal Characteristics 1a 1b R Thermal Resistance, Junction to Ambient 60 56 JA 1c 1d R Thermal Resistance, Junction to Ambient 150 140 C/W JA R Thermal Resistance, Junction to Case 4 3.5 JC Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDML7610S FDML7610S MLP3X4.5 13 12 mm 3000 units 1 2013 Fairchild Semiconductor Corporation www.fairchildsemi.com FDML7610S Rev.C1