EVBUM2275/D KAI-2001 / KAI-2020 / KAI-2093 Imager Board User s Manual Description The KAI2001/KAI2020/KAI2093 Imager Evaluation www.onsemi.com Board, referred to in this document as the Imager Board, is designed to be used as part of a twoboard set, used in EVAL BOARD USERS MANUAL conjunction with a Timing Generator Board. ONSemiconductor offers an Imager Board / Timing Generator Board package that has been designed and configured to operate with the KAI2001, KAI 2020, and KAI2093 Image Sensors. The Timing Generator Board generates the timing signals For testing and characterization purposes, the Imager necessary to operate the CCD, and provides the power Board provides the ability to adjust many of the CCD bias required by the Imager Board. The timing signals, in LVDS voltages and CCD clock level voltages by adjusting format, and the power, are provided to the Imager Board via potentiometers on the board. The Imager Board provides the the interface connector (J4). In addition, the Timing means to modify other device operating parameters (e.g., Generator Board performs the processing and digitization of CCD reset clock pulse width) by populating components the analog video output of the Imager Board. differently on the board. The Imager Board has been designed to operate Some circuitry on the Imager Board (e.g., remote DAC KAI2001, KAI 2020, and KAI 2093 with the specified control of bias and clock level voltages) is intended for performance at nominal operating conditions. (See the ON Semiconductor test purposes only, and may not be appropriate performance specifications for details). populated. INPUT REQUIREMENTS Table 1. POWER REQUIREMENTS Power Supplies Minimum Typical Maximum Units 4.9 5.0 5.1 V +5 V MTR Supply 800 mA 5 V MTR Supply 5.1 5.0 4.9 V 200 mA VPLUS Supply 18 20 21 V 250 mA VMINUS Supply 21 20 18 V 250 mA Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) V V V Units Signal Comments min threshold max IMAGER IN0 0 0.1 2.4 V AMP ENABLE Output Amplifier Enable IMAGER IN1 0 0.1 2.4 V H1A H1A clock IMAGER IN2 0 0.1 2.4 V H1B H1B clock IMAGER IN3 0 0.1 2.4 V H2A H2A clock IMAGER IN4 0 0.1 2.4 V H2B H2B clock IMAGER IN5 0 0.1 2.4 V RESET Reset clock IMAGER IN6 0 0.1 2.4 V V1 V1 clock Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 Rev. 2 EVBUM2275/DEVBUM2275/D Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) V V V Units Signal Comments min threshold max IMAGER IN7 0 0.1 2.4 V V2 V2 clock IMAGER IN8 0 0.1 2.4 V (not used) rd IMAGER IN9 0 0.1 2.4 V V3RD V2 Clock 3 level IMAGER IN10 0 0.1 2.4 V FDG Fast Dump clock IMAGER IN11 0 0.1 2.4 V VES Electronic Shutter clock ARCHITECTURE OVERVIEW The following sections describe the functional blocks of frame to transfer the charge from the photodiodes to the the Imager Board (Refer to Figure 1). vertical CCDs. The V1 clock driver is a 2level driver circuit, switching Power Filtering and Regulation between VMID and VLOW voltage levels. Power is supplied to the Imager Board via the J4 interface connector. The power supplies are de coupled and filtered CCD FDG Driver with ferrite beads and capacitors to suppress noise. Voltage The Fast Dump clock drivers consist of a transistor that regulators are used to create the +15 V and 15 V supplies will switch the voltage on the FD pin of the CCD from from the VPLUS and VMINUS supplies. FDG LOW to FDG HIGH during Fast Dump Gate operations. When not in operation, or when the Fast Dump LVDS Receivers / TTL Buffers Gate feature is not being utilized, the FDG pin of the CCD LVDS timing signals are input to the Imager Board via the is held at FDG LOW. The FDG HIGH and FDG LOW J4 interface connector. These signals are shifted to TTL voltage levels of the FDG driver are set by potentiometers, levels before being sent to the CCD clock drivers. buffered by operational amplifiers configured as voltage followers. The KAI2093 image sensor does not have the CCD PixelRate Clock Drivers (H1, H2 & Reset Clocks) Fast Dump Gate feature. To support this device, the Imager The pixel rate CCD clock drivers utilize two fast Board must be configured so that the CCD pin 11 is 0.0 V. switching transistors that are designed to translate To accomplish this, R91 is removed, and R79 is installed. TTLlevel input clock signals to the voltage levels required by the CCD. The high level and low levels of the CCD clocks VSUB/VES Circuit are set by potentiometers, and are buffered by operational The quiescent CCD substrate voltage (VSUB) is set by a amplifiers configured as voltage followers. potentiometer and resistor divider network. The VSUB voltage is buffered by an operational amplifier configured Reset Clock OneShot with a gain of 1.40, to allow the voltage to be adjusted to The pulse width of the RESET CCD clock may be set by nearly 14.0 V. A blocking diode prevents the VSUB bias U13, a programmable OneShot. The OneShot can be circuitry from being damaged by the highervoltage configured to provide a RESET CCD clock signal with a electronic shutter pulse. pulse width from 5 ns to 15 ns. If pulse width control For electronic shutter operation, the VES signal drives a functionality is provided by the Timing Board, the transistor amplifier circuit that ACcouples the voltage OneShot may be removed and bypassed by installing difference between the VPLUS and VMINUS supplies onto R147. the Substrate voltage. This creates the necessary potential to CCD VCLK Drivers clear all charge from the photodiodes, thereby acting as an The vertical clock (VCLK) drivers consist of MOSFET electronic shutter to control exposure. driver ICs. These drivers are designed to translate the VDD Bias Voltage TTLlevel clock signals to the voltage levels required by the The VDDL and VDDR video output amplifier supplies in CCD. The high, middle, and low voltage levels of the the CCD are coupled directly to the +15 V regulated supply vertical clocks are set by potentiometers buffered by on the Imager Board. The Imager Board contains optional operational amplifiers. The VHIGH and VLOW opamps circuitry that allows this voltage to be adjusted through the have a gain of 1.25, to allow the magnitude of the voltages Alternate VDD bias circuit. to be adjusted to 12.5 V when using DAC control. The Imager Board contains optional Amplifier Enable The current sources for these voltage levels are high circuitry to control a switch that switches the VDD voltage current (up to 600 mA) transistors. The V2 CCD high level from +15 V to ALT VDD. clock voltage is switched from V MID to V HIGH once per