Ordering number : EN7257B LB11872H Monolithic Digital IC For Polygonal Mirror Motors LB11872H Allowable Operating Conditions at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage range V 10 to 28 V CC 6.3 V regulator-voltage output current IREG 0 to -20 mA LD pin applied voltage VLD 0 to 28 V LD pin output current ILD 0 to 15 mA FGS pin applied voltage VFG 0 to 28 V FGS pin output current IFG 0 to 10 mA Electrical Characteristics at Ta = 25C, V = VM = 24V CC Ratings Parameter Symbol Conditions Unit min typ max Supply current 1 I1 Stop mode 5 7 mA CC Supply current 2 I2 Start mode 17 22 mA CC Output saturation voltages VAGC = 3.5V SOURCE (1) VSAT1-1 I = 0.5A, RF = 0 1.7 2.2V O SOURCE (2) VSAT1-2 I = 1.0A, RF = 0 2.0 2.7V O SINK (1) VSAT2-1 I = 0.5A, RF = 0 0.4 0.9V O SINK (2) VSAT2-2 I = 1.0A, RF = 0 1.0 1.7V O Output leakage current I (LEAK) V = 28V 100 A O CC 6.3V Regulator-voltage output Output voltage VREG 5.90 6.25 6.60 V Voltage regulation VREG1 V = 9.5 to 28V 50 100 mV CC Load regulation VREG2 Iload = -5 to -20mA 10 60 mV 1 Temperature coefficient VREG3 Design target value* 0 mV/C Hall amplifier block Input bias current IB (HA) Differential input : 50mVp-p 2 10 A Differential input voltage range VH SIN wave input 50 *600 mVp-p IN Common-phase input voltage range VICM Differential input : 50mVp-p 2.0 V -2.5 V CC 1 Input offset voltage VIOH Design target value* -20 20mV FG amplifier and schmitt block (IN1) Input amplifier gain GFG 5 Times Input hysteresis (high to low) VSHL 0 mV Input hysteresis (low to high) VSLH -10 mV Hysteresis width VFGL Input conversion 4 7 12 mV Low-voltage protection circuit Operating voltage VSD 8.4 8.8 9.2 V Hysteresis width VSD 0.2 0.4 0.6 V Thermal protection circuit 1 Thermal shutdown operating TSD Design target value* (junction temperature) 150 180 C temperature 1 Hysteresis width TSD Design target value* (junction temperature) 40 C Current limiter operation Acceleration limit voltage VRF1 0.53 0.59 0.65 V Deceleration limit voltage VRF2 0.32 0.37 0.42 V Error amplifier 1 Input offset voltage VIO (ER) Design target value* -10 10mV Input bias current IB (ER) -1 1 A High-level output voltage V (ER) I = -500A VREG-1.2VREG-0.9 V OH OH Low-level output voltage V (ER) I = 500A 0.9 1.2V OL OL DC bias level VB (ER) -5% 1/2VREG 5% V Note* : Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input. amplitudes should be held to under 350mVp-p. 1 * : This parameter is a design target value and is not measured. Continued on next page. No.7257-2/11