MC100EL13 5 VECL Dual 1:3 Fanout Buffer The MC100EL13 is a dual, fully differential 1:3 fanout buffer. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. www.onsemi.com The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V , The D input will bias around EE V /2 and the Q output will go LOW. CC Features 500 ps Typical Propagation Delays SOIC20 WB 50 ps Output-Output Skews DW SUFFIX CASE 751D05 The 100 Series Contains Temperature Compensation PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V CC EE MARKING DIAGRAM* NECL Mode Operating Range: 20 V = 0 V with V = 4.2 V to 5.7 V CC EE Internal Input Pulldown Resistors 100EL13 AWLYYWWG Q Output will Default LOW with Inputs Open or at V EE Internal Input Pulldown Resistors on All Inputs, Pullup Resistors on Inverted Inputs 1 These Devices are Pb-Free, Halogen Free and are RoHS Compliant A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EL13DWG SOIC20 WB 38 Units/Tube (Pb-Free) MC100EL13DWR2G SOIC20 WB 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 7 MC100EL13/DMC100EL13 Q1a Q1a Q2a Q2a V Q2b Q2b Q1b Q1b V Table 1. PIN DESCRIPTION CC EE 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION Qna, Qna ECL Differential Clock Outputs Qnb, Qnb ECL Differential Clock Outputs CLKn, CLKn ECL Differential Clock Inputs V Positive Supply CC VEE Negative Supply 1 2 3 4 5678 9 10 Q0a Q0a V CLKa CLKa CLKb CLKb Q0b Q0b CC V CC * All V pins are tied together on the die. CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: Assignment Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charge Device Model > 4 kV Moisture Sensitivity (Note 1) Level 3 Pb-Free Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 143 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder (Pb-Free) <2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2