MC100EL56 5 VECL Dual Differential 2:1 Multiplexer Description The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low www.onsemi.com skew clock or other skew sensitive signals. Multiple V pins are BB provided to ease AC coupling input signals. The V pins, an internally generated voltage supply, are available BB to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC SOIC20 WB to 0.5 mA. When not used, V should be left open. BB DW SUFFIX The device features both individual and common select inputs to CASE 751D05 address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs MARKING DIAGRAM* are left open, the D input will pull down to V . The D input will bias EE around V /2 forcing the Q output LOW. CC 20 Features 580 ps Typical Propagation Delays 100EL56 Separate and Common Select AWLYYWWG The 100 Series Contains Temperature Compensation PECL Mode Operating Range: 1 V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: A = Assembly Location WL = Wafer Lot V = 0 V with V = 4.2 V to 5.7 V CC EE YY = Year Internal Input Pulldown Resistors on D(s), SEL(s), and COM SEL WW = Work Week Q Output will Default LOW with Inputs Open or at V G = Pb-Free Package EE These Devices are Pb-Free, Halogen Free and are RoHS Compliant *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EL56DWG SOIC20 WB 38 Units/Tube (Pb-Free) MC100EL56DWR2G SOIC20 wB 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 9 MC100EL56/DMC100EL56 Table 1. PIN DESCRIPTION PIN FUNCTION D0a* D1a* ECL Input Data a V Q0 Q0 SEL0 V Q1 Q1 V D0a* D1a* ECL Input Data a Invert SEL1 CC CC EE D0b* D1b* ECL Input Data b 20 19 18 17 16 15 14 13 12 11 D0b* D1b* ECL Input Data b Invert SEL0* SEL1* ECL Indiv. Select Input COM SEL* ECL Common Select Input V , V Output Reference Voltage BB0 BB1 Q0 Q1 ECL True Outputs 10 1 0 Q0 Q1 ECL Inverted Outputs V Positive Supply CC V Negative Supply EE * Pins will default LOW when left open. 1 2 3 4 56 78 9 10 D0a D0a V D0b D0b D1a D1a V D1b D1b BBO BB1 Table 2. TRUTH TABLE Warning: All V and V pins must be externally connected CC EE Q0, Q1, to Power Supply to guarantee proper operation. SEL0 SEL1 COM SEL Q0 Q1 X X H a a Figure 1. 20-Lead Package (Top View) and Logic Diagram L L L b b L H L b a H H L a a H L L a b Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charge Device Model > 4 kV Moisture Sensitivity (Note 1) Level 3 Pb-Free Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 147 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information. www.onsemi.com 2 COM SEL