3.3 V/5 VECL 6-Bit Differential Register with Master Reset MC10EP451, MC100EP451 Description www.onsemi.com The MC10/100EP451 is a 6 bit fully differential register with common clock and singleended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75 k pulldown resistor internally. Differential 1 32 inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < V + 1.2 V, the clamp will override and force the output to LQFP32 QFN32 EE FA SUFFIX MN SUFFIX a default state. When in the default state, and since the flipflop is edge CASE 561AB CASE 488AM triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK (pin 4) will latch the registers. MARKING DIAGRAMS* Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW. The 100 Series contains temperature compensation. 1 MCxx MCxxx Features EP451 EP451 450 ps Typical Propagation Delay AWLYYWW AWLYYWWG Maximum Frequency > 3.0 GHz Typical Asynchronous Master Reset 20 ps Skew Within Device, 35 ps Skew DeviceToDevice xxx = 10 or 100 PECL Mode Operating Range: V = 3.0 V to 5.5 V CC A = Assembly Location With V = 0 V WL = Wafer Lot EE YY = Year NECL Mode Operating Range: V = 0 V CC WW = Work Week With V = 3.0 V to 5.5 V EE G or = PbFree Package Open Input Default State (Note: Microdot may be in either location) Safety Clamp on Inputs *For additional marking information, refer to These Devices are PbFree and are RoHS Compliant Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping LQFP32 250 Units / Tube MC10EP451FAG (PbFree) LQFP32 250 Units / Tube MC100EP451FAG (PbFree) LQFP32 2000 / MC100EP451FAR2G (PbFree) Tape & Reel QFN32 72 Units / Tube MC100EP451MNG (PbFree) QFN32 1000 / MC100EP451MNR4G (PbFree) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2021 Rev. 11 MC10EP451/DMC10EP451, MC100EP451 D4 D5 D5 Q5 Q5 V Q4 Q4 EE D1 D2 D2 MR V D3 D3 D4 EE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 25 16 D4 V 1 CC D1 24 D4 26 15 D3 Q3 D0 2 23 D5 27 14 D3 Q3 22 D5 D0 3 28 13 V V 4 21 Q5 CLK EE CC MC10EP451 MC10EP451 MC100EP451 MC100EP451 29 12 5 20 MR Q2 CLK Q5 30 11 6 D2 Q2 V 19 V EE CC 31 10 Q0 7 D2 Q1 18 Q4 32 9 Q0 8 17 Q4 D1 Q1 123456 78 9 10 11 12 13 14 15 16 Q1 Q1 Q2 Q2 V Q3 Q3 V CC CC Figure 2. QFN32 Pinout (Top View) D1 D0 D0 CLK CLK V Q0 Q0 CC Warning: All V and V pins must be externally connected to Power CC EE Supply to guarantee proper operation. D0 Q Q0 D Figure 1. LQFP32 Pinout (Top View) D0 Q0 R Table 1. PIN DESCRIPTION D1 Q D Q1 PIN FUNCTION D1 Q1 D 0:5 *, D 0:5 * ECL Differential Data Inputs R MR* ECL Master Reset Input CLK*, CLK* ECL Differential Clock Inputs D2 Q 0:5 , Q 0:5 ECL Differential Data Outputs D Q Q2 D2 Q2 V Positive Supply CC V Negative Supply R EE EP for QFN32, The Exposed Pad (EP) on the only QFN32 package bottom is D3 Q Q3 D thermally connected to the die D3 for improved heat transfer out Q3 of package. The exposed pad must be attached to a heat R sinking conduit. The pad is electrically connected to V . EE D4 Q D Q4 * Pins will default LOW when left open. D4 Q4 R D5 Q D Q5 D5 Q5 CLK R CLK V EE MR Figure 3. Logic Diagram www.onsemi.com 2