MC100EP51DR2G ON Semiconductor

MC10EP51, MC100EP51 3.3V / 5VECL D Flip-Flop with Reset and Differential Clock Description MC10EP51, MC100EP51 Table 1. PIN DESCRIPTION PIN FUNCTION RESET 1 8 V CC CLK*, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset R D* ECL Data Input D 2 7 Q D Q, Q ECL Data Outputs V Positive Supply CC Flip-Flop V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a suf- ficient thermal conduit. Electric- ally connect to the most negative supply (GND) or leave uncon- nected, floating open. CLK45 V EE * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8Lead Pinout (Top View) and Logic Diagram D R CLK Q L L Z L H L Z H X H X L Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg SOIC8 Level 1 Level 1 TSSOP8 Level 1 Level 3 DFN8 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 165 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.