3.3 V/5 VECL Differential Data and Clock D FlipFlop MC10EP52, MC100EP52 Description The MC10EP/100EP52 is a differential data, differential clock D www.onsemi.com flip-flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flipflop when the clock is 8 8 LOW and is transferred to the slave, and thus the outputs, upon a 1 1 positive transition of the clock. The differential clock inputs of the SOIC8 NB TSSOP8 DFN8 EP52 allow the device to also be used as a negative edge triggered D SUFFIX DT SUFFIX MN SUFFIX device. CASE 75107 CASE 948R02 CASE 506AA The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V ) the outputs of the device will remain MARKING DIAGRAMS* EE stable. 8 The 100 Series contains temperature compensation. HP52 ALYW Features 330 ps Typical Propagation Delay 1 Maximum Frequency = 4 GHz Typical 8 8 PECL Mode: V = 3.0 V to 5.5 V with V = 0 V CC EE KEP52 KP52 NECL Mode: V = 0 V with V = 3.0 V to 5.5 V CC EE ALYW ALYW Open Input Default State 14 1 1 Safety Clamp on Inputs Q Output Will Default LOW with Inputs Open or at V SOIC8 NB TSSOP8 DFN8 EE These Devices are Pb-Free, Halogen Free and are RoHS Compliant H = MC10 L = Wafer Lot K = MC100 Y = Year 3O = MC100 W = Work Week M = Date Code = PbFree Package A = Assembly Location (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Package Device Shipping TSSOP8 100 Units / MC10EP52DTG (Pb-Free) Tube SOIC8 NB 98 Units / MC100EP52DG (Pb-Free) Tube SOIC8 NB 2500 Tape & MC100EP52DR2G (Pb-Free) Reel TSSOP8 100 Units / MC100EP52DTG (Pb-Free) Tube MC100EP52DTR2G TSSOP8 2500 Tape & (Pb-Free) Reel DFN8 1000 / Tape & MC100EP52MNR4G (Pb-Free) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifica- tions Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: April, 2021 Rev. 9 MC10EP52/D 3OM MC10EP52, MC100EP52 Table 1. PIN DESCRIPTION D 1 8 V CC PIN FUNCTION CLK*, CLK* ECL Clock Inputs D*, D* ECL Data Input D D 2 7 Q Q, Q ECL Data Outputs V Positive Supply CC Flip-Flop V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. CLK45 V EE * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram D CLK Q L Z L H Z H Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 155 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2