Product Information

MC100EP56DWR2G

MC100EP56DWR2G electronic component of ON Semiconductor

Datasheet
Clock Multiplexer 2-OUT 20-Pin SOIC W T/R
Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

57: USD 7.723 ea
Line Total: USD 440.21

0 - Global Stock
MOQ: 57  Multiples: 57
Pack Size: 57

 More Buying Options & Price Grid(s)

Availability Price Quantity
0 - Global Stock


Ships to you between Thu. 02 May to Wed. 08 May

MOQ : 57
Multiples : 57

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MC100EP56DWR2G
ON Semiconductor

57 : USD 7.4853

0 - Global Stock


Ships to you between Thu. 02 May to Wed. 08 May

MOQ : 1000
Multiples : 1000

Stock Image

MC100EP56DWR2G
ON Semiconductor

1000 : USD 8.4962

Read More Specifications

     
Manufacturer
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RoHS - XON
Icon ROHS
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Logic Family
Number of Input Lines
Number of Output Lines
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
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Additional Infomation About Product

MC10EP56, MC100EP56 3.3V / 5VECL Dual Differential 2:1 Multiplexer Description The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low MC10EP56, MC100EP56 Table 1. PIN DESCRIPTION PIN FUNCTION D0a* D1a* ECL Input Data a V Q0 Q0 SEL0 V Q1 Q1 V CC SEL1 CC EE D0a* D1a* ECL Input Data a Invert 20 19 18 17 16 15 14 13 12 11 D0b* D1b* ECL Input Data b D0b* D1b* ECL Input Data b Invert SEL0* SEL1* ECL Indiv. Select Input COM_SEL* ECL Common Select Input V , V Output Reference Voltage BB0 BB1 10 1 0 Q0 Q1 ECL True Outputs Q0 Q1 ECL Inverted Outputs V Positive Supply CC V Negative Supply EE EP Exposed Pad 1 2 3 4 5 678 9 10 D0a D0a V D0b D0b D1a D1a V D1b D1b * Pins will default LOW when left open. BBO BB1 Warning: All V and V pins must be externally connected CC EE Table 2. TRUTH TABLE to Power Supply to guarantee proper operation. Q0, Q1, Figure 1. 20Lead Package (Top View) and Logic Diagram SEL0 SEL1 COM_SEL Q0 Q1 X X H a a L L L b b L H L b a H H L a a H L L a b Exposed Pad D0a D0a V Q0 Q0 CC 20 19 18 17 16 V 1 15 SEL0 BB0 D0b 2 14 COM_SEL D0b MC10/100EP56 3 13 SEL1 4 D1a 12 V CC D1a 5 11 Q1 67 8 9 10 V D1b D1b V Q1 BB1 EE NOTE: The Exposed Pad (EP) on package bottom must be attached to a heatsinking conduit. The Exposed Pad may only be electrically connected to V . EE Figure 1. QFN20 Pinout (Top View)

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

ON Semiconductor may also be referenced as

Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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