2.5 V/3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL Output Translator MC100EP91 www.onsemi.com Description The MC100EP91 is a triple any level positive input to NECL output 20 translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL 24 1 1 output signals (3.0 V/5.5 V). SOIC20 WB QFN24 To accomplish the level translation the EP91 requires three power DW SUFFIX MN SUFFIX rails. The V pins should be connected to the positive power supply, CC CASE 751D CASE 485L and the V pin should be connected to the negative power supply. EE The GND pins are connected to the system ground plane. Both V EE and V should be bypassed to ground via 0.01 F capacitors. MARKING DIAGRAMS* CC Under open input conditions, the D input will be biased at V /2 CC 24 and the D input will be pulled to GND. These conditions will force the 20 1 Q outputs to a low state, and Q outputs to a high state, which will 100 MC100EP91 EP91 ensure stability. AWLYYWWG ALYW The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused 1 differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V SOIC20 WB QFN24 BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC A = Assembly Location to 0.5 mA. When not used, V should be left open. BB WL, L = Wafer Lot YY, Y = Year WW, W = Work Week Features G or = Pb-Free Package Maximum Input Clock Frequency = > 2.0 GHz Typical (Note: Microdot may be in either location) Maximum Input Data Rate = > 2.0 Gb/s Typical *For additional marking information, refer to 500 ps Typical Propagation Delay Application Note AND8002/D. Operating Range: V = 2.375 V to 3.8 V V = 3.0 V to 5.5 V GND = 0 V CC EE ORDERING INFORMATION Q Output will Default LOW with Inputs Open or at GND These Devices are Pb-Free, Halogen Free and are RoHS Compliant Device Package Shipping MC100EP91DWG SOIC20 WB 38 Units / Tube (Pb-Free) MC100EP91DWR2G 1000 Tape & Reel SOIC20 WB (Pb-Free) MC100EP91MNG QFN24 92 Units / Tube (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 7 MC100EP91/DMC100EP91 Positive Level NECL Output Input D0 Q0 R1 R2 D0 Q0 R1 D1 Q1 R1 R2 V CC D1 Q1 V BB R1 GND D2 Q2 R1 V EE R2 D2 Q2 R1 Figure 1. Logic Diagram Table 1. PIN DESCRIPTION Pin Default SOIC QFN Name I/O State Description 1, 20 3, 4, 12 V Positive Supply Voltage. All V Pins must be Externally CC CC Connected to Power Supply to Guarantee Proper Operation 10 15, 16 V Negative Supply Voltage. All V Pins must be Externally EE EE Connected to Power Supply to Guarantee Proper Operation 14, 17 19, 20, 23, GND Ground 24 4, 7 7, 11 V ECL Reference Voltage Output BB 2, 5, 8 5, 8, 13 D 0:2 LVPECL, LVDS, LVTTL, Low Noninverted Differential Inputs 0:2 . Internal 75 k to GND. LVCMOS, CML, HSTL Input 3, 6, 9 6, 9, 14 D 0:2 LVPECL, LVDS, High Inverted Differential Inputs 0:2 . Internal 75 k to GND and LVTTL,LVCMOS, CML, 75 k to V . When Inputs are Left Open They Default to CC HSTL Input (V GND) / 2 CC 19,16,13 2, 22, 18 Q 0:2 NECL Output Noninverted Differential Outputs 0:2 . Typically Terminated with 50 to V = V 2 V TT CC 18,15,12 1, 21, 17 Q 0:2 NECL Output Inverted Differential Outputs 0:2 . Typically Terminated with 50 to V = V 2 V TT CC 11 10 NC No Connect. The NC Pin is NOT Electrically Connected to the Die and may Safely be Connected to Any Voltage from V to V EE CC N/A EP Exposed Pad (Note 1) 1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heatsinking conduit and may only be electrically connected to V (not GND). EE www.onsemi.com 2