MC100LVEL11 3.3VECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance www.onsemi.com capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for MARKING those applications which require the ultimate in AC performance. DIAGRAMS* The differential inputs of the LVEL11 employ clamping circuitry to 8 maintain stability under open input conditions. If the inputs are left 8 1 open (pulled to V ) the Q outputs will go LOW. KVL11 EE ALYW Features SOIC8 D SUFFIX 1 330 ps Propagation Delay CASE 751 5 ps Skew Between Outputs High Bandwidth Output Transitions 8 8 The 100 Series Contains Temperature Compensation 1 KV11 ALYW PECL Mode Operating Range: V = 3.0 V to 3.8 V CC TSSOP8 with V = 0 V EE DT SUFFIX 1 NECL Mode Operating Range: V = 0 V CASE 948R CC with V = 3.0 V to 3.8 V EE Internal Input Pulldown Resistors on D, 1 Pullup and Pulldown Resistors on D 3ZM Q Output will Default LOW with Inputs Open or at V EE 1 These Devices are PbFree and are RoHS Compliant DFN8 MN SUFFIX CASE 506AA Q 1 8 V 0 CC A = Assembly Location L = Wafer Lot Y = Year Q 2 7 D 0 W = Work Week M = Date Code = PbFree Package (Note: Microdot may be in either location) Q 3 6 D 1 *For additional marking information, refer to Application Note AND8002/D. Q 4 5 V 1 EE ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Figure 1. Logic Diagram and Pinout Assignment Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: January, 2015 Rev. 13 MC100LVEL11/DMC100LVEL11 Table 1. PIN DESCRIPTION Pin Function Q0, Q0 Q1, Q1 ECL Data Outputs D, D ECL Data Inputs V Positive Supply CC V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a suffi- cient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 4 KV Machine Model > 400 V Charge Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC8 Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 63 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 to 0 CC I EE I Output Current Continuous 50 mA out Surge 100 mA T Operating Temperature Range 40 to +95 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (JunctiontoAmbient) 0 lpfm SOIC8 190 C/W JA 500 lpfm SOIC8 130 C/W Thermal Resistance (JunctiontoCase) Standard Board SOIC8 41 to 44 5% C/W JC Thermal Resistance (JunctiontoAmbient) 0 lpfm TSSOP8 185 C/W JA 500 lpfm TSSOP8 140 C/W Thermal Resistance (JunctiontoCase) Standard Board TSSOP8 41 to 44 5% C/W JC Thermal Resistance (JunctiontoAmbient) 0 lfpm DFN8 129 C/W JA 500 lfpm DFN8 84 C/W T Wave Solder PbFree <2 to 3 sec 260C 265 C sol Thermal Resistance (JunctiontoCase) (Note 2) DFN8 35 to 40 C/W JC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board 2S2P (2 signal, 2 power) www.onsemi.com 2