Product Information

MC100LVEL56DWR2G

MC100LVEL56DWR2G electronic component of ON Semiconductor

Datasheet
Encoders, Decoders, Multiplexers & Demultiplexers 3.3V ECL Dual Diff 2:1 Mux
Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
N/A

Obsolete

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Availability Price Quantity
0 - Warehouse 1

MOQ : 1000
Multiples : 1000

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MC100LVEL56DWR2G
ON Semiconductor

1000 : USD 4.5811
N/A

Obsolete
0 - Warehouse 2

MOQ : 66
Multiples : 66

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MC100LVEL56DWR2G
ON Semiconductor

66 : USD 6.3752
N/A

Obsolete
0 - Warehouse 3

MOQ : 1
Multiples : 1

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MC100LVEL56DWR2G
ON Semiconductor

1 : USD 8.7525
10 : USD 7.6788
25 : USD 7.452
100 : USD 6.5448
250 : USD 6.3504
500 : USD 5.8644
1000 : USD 5.6916
2000 : USD 5.5188
N/A

Obsolete
0 - Warehouse 4

MOQ : 1000
Multiples : 1000

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MC100LVEL56DWR2G
ON Semiconductor

1000 : USD 6.2053
N/A

Obsolete

Read More Specifications

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Family
Number of Input Lines
Number of Output Lines
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
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Additional Infomation About Product

MC100LVEL56 3.3 VECL Dual Differential 2:1 Multiplexer Description The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew www.onsemi.com clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V , The D input will bias EE around V /2 forcing the Q output LOW. CC SOIC20 WB The V pin, an internally generated voltage supply, is available to BB DW SUFFIX this device only. For single-ended input conditions, the unused CASE 751D differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V and BB BB V via a 0.01 F capacitor and limit current sourcing or sinking to CC MARKING DIAGRAM* 0.5 mA. When not used, V should be left open. BB Features 20 580 ps Typical Propagation Delays Separate and Common Select 100LVEL56 AWLYYWWG The 100 Series Contains Temperature Compensation PECL Mode Operating Range: V = 3.0 V to 3.8 V with V = 0 V CC EE 1 NECL Mode Operating Range: V = 0 V with V = 3.0 V to 3.8 V A = Assembly Location CC EE WL = Wafer Lot Internal Input Pulldown Resistors on D(s), SEL(s), and COM SEL YY = Year Q Output will Default LOW with Inputs Open or at V EE WW = Work Week G = Pb-Free Package These Devices are Pb-Free, Halogen Free and are RoHS Compliant *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100LVEL56DWG SOIC20 WB 38 Units/Tube (Pb-Free) MC100LVEL56DWR2G SOIC20 WB 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 13 MC100LVEL56/DMC100LVEL56 Table 1. PIN DESCRIPTION PIN FUNCTION D0a* D1a* ECL Input Data a V Q0 Q0 SEL0 V Q1 Q1 V SEL1 CC CC EE D0a* D1a* ECL Input Data a Invert 20 19 18 17 16 15 14 13 12 11 D0b* D1b* ECL Input Data b D0b* D1b* ECL Input Data b Invert SEL0* SEL1* ECL Indiv. Select Input COM SEL* ECL Common Select Input V , V Output Reference Voltage BB0 BB1 10 1 0 Q0 Q1 ECL True Outputs Q0 Q1 ECL Inverted Outputs V Positive Supply CC V Negative Supply EE * Pins will default LOW when left open. 1 2 3 4 5 678 9 10 Table 2. TRUTH TABLE D0a D0a V D0b D0b D1a D1a V D1b D1b BBO BB1 Q0, Q1, Warning: All V and V pins must be externally connected CC EE SEL0 SEL1 COM SEL Q0 Q1 to Power Supply to guarantee proper operation. X X H a a L L L b b Figure 1. 20-Lead Package (Top View) and Logic Diagram L H L b a H H L a a H L L a b Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 K Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Device Model > 4 kV Moisture Sensitivity, (Note 1) Pb-Free Level 3 Flammability Rating UL 94 V0 0.125 in Oxygen Index 28 to 34 Transistor Count 147 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 COM SEL

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

ON Semiconductor may also be referenced as

Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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