MC100LVEP210MNG ON Semiconductor

MC100LVEP210 2.5V / 3.3V1:5 Dual Differential ECL/PECL/HSTL Clock Driver Description 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1234567 8 MC100LVEP210 Exposed Pad V Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V (EP) CC CC V Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V CC CC 32 31 30 29 28 27 26 25 1 V Qa3 V 24 CC Qa3 CC NC Qa3 NC 2 23 Qa3 Qa4 CLKa CLKa 22 3 Qa4 Qa4 CLKa CLKa 4 21 Qa4 MC100LVEP210 MC100LVEP210 V V Qb0 BB BB Qb0 5 20 CLKb CLKb Qb0 Qb0 6 19 Qb1 CLKb CLKb Qb1 7 18 V V Qb1 EE EE Qb1 8 17 9 10 11 12 13 14 15 16 V Qb4 Qb4Qb3 Qb3 Qb2 Qb2 V CC CC V Qb4 Qb4Qb3 Qb3 Qb2 Qb2 V CC CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 2. LQFP32 Pinout (Top View) Figure 1. 32Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLKn*, CLKn** ECL/PECL/HSTL CLK Inputs Qn0:4, Qn0:4 ECL/PECL Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE EP The exposed pad (EP) on the QFN32 package bottom is thermally connected to the die for im- proved heat transfer out of the package. THe exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to V . EE * Pins will default LOW when left open. ** Pins will default to V /2 when left open. CC Qa0 Qb0 Qa0 Qb0 Qb1 Qa1 CLKa CLKb Qa1 Qb1 CLKa CLKb Qb2 Qa2 Qa2 Qb2 Qa3 Qb3 V BB Qa3 Qb3 V Qa4 CC Qb4 V EE Qa4 Qb4 Figure 3. Logic Diagram