MC10E158FNG

MC10E158, MC100E158 5VECL 5Bit 2:1 Multiplexer Description The MC10E/100E158 contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input (SEL). www.onsemi.com The 100 Series contains temperature compensation. Features 600 ps Max. D to Output 800 ps Max. SEL to Output Differential Outputs One V Pin Per Output Pair CCO PLCC28 FN SUFFIX PECL Mode Operating Range: CASE 77602 V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V CC EE MARKING DIAGRAM* Internal Input 50 k Pulldown Resistors 1 ESD Protection: Human Body Model; > 2 kV Machine Model; > 200 V MCxxxE158FNG Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test AWLYYWW Moisture Sensitivity Level: 3 (Pb-Free) For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V0 @ 0.125 in, Oxygen Index: 28 to 34 xxx = 10 or 100 A = Assembly Location Transistor Count = 126 devices WL = Wafer Lot These Devices are Pb-Free, Halogen Free and are RoHS Compliant YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC10E158FNG PLCC28 37 Units/Tube (Pb-Free) MC10E158FNR2G PLCC28 500/Tape & Reel (Pb-Free) MC100E158FNG PLCC28 37 Units/Tube (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 10 MC10E158/DMC10E158, MC100E158 D a D b D a V Q Q V 4 3 3 CCO 4 4 CCO D a MUX Q 0 0 25 24 23 22 21 20 19 Q SEL D b 0 0 18 Q D b 3 26 4 Q MUX D a 1 1 17 Q D a 3 27 2 Q SEL 1 D b 1 D b 28 16 V CC 2 Pinout: 28-Lead PLCC D a 2 Q MUX 2 V 1 15 Q 2 EE (Top View) D b Q 2 SEL 2 SEL 2 14 Q 2 D a MUX 3 Q 3 D a 3 13 V 0 CCO Q D b SEL 3 3 D b 4 Q 0 12 1 D a MUX 4 Q 4 567 89 10 11 Q SEL D b 4 4 DaDbV Q Q V Q 1 1 CCO 0 0 CCO 1 * All V and V pins are tied together on the die. CC CCO SEL Warning: All V , V , and V pins must be externally CC CCO EE connected to Power Supply to guarantee proper operation. Figure 2. Logic Diagram Figure 1. 28-Lead Pinout Table 1. PIN DESCRIPTION PIN FUNCTION D a D a ECL Input Data a 0 4 D b D b ECL Input Data b 0 4 Q Q ECL True Outputs 0 4 Q Q ECL Inverted Outputs 0 4 SEL ECL Select Input V , V Positive Supply CC CCO V Negative Supply EE Table 2. Logic Diagram SEL Data H a L b www.onsemi.com 2