MC10EL51, MC100EL51 5 VECL Differential Clock D FlipFlop Description The MC10EL/100EL51 is a differential clock D flip-flop with reset. The device is functionally similar to the E151 device with higher www.onsemi.com performance capabilities. With propagation delays and output transition times significantly faster than the E151 the EL51 is ideally suited for those applications which require the ultimate in AC 8 performance. 8 1 The reset input is an asynchronous, level triggered signal. Data 1 enters the master portion of the flip-flop when the clock is LOW and is SOIC8NB TSSOP8 transferred to the slave, and thus the outputs, upon a positive transition D SUFFIX DT SUFFIX of the clock. The differential clock inputs of the EL51 allow the device CASE 75107 CASE 948R02 to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input (pulled down to V ) conditions. EE MARKING DIAGRAMS* The 100 Series contains temperature compensation. 8 8 Features HEL51 HL51 475 ps Propagation Delay ALYW ALYW 2.8 GHz Toggle Frequency ESD Protection: 1 1 > 1 kV Human Body Model 8 8 > 100 V Machine Model KEL51 KL51 PECL Mode Operating Range: ALYW ALYW V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: 1 1 V = 0 V with V = 4.2 V to 5.7 V CC EE H = MC10 L = Wafer Lot K = MC100 Y = Year Internal Input Pulldown Resistors on D, R, and CLK 4X = MC10 W = Work Week Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2M= MC100 M = Date Code Moisture Sensitivity: A = Assembly Location = Pb-Free Package Level 1 for SOIC8NB (Note: Microdot may be in either location) Level 3 for TSSOP8 *For additional marking information, refer to For Additional Information, see Application Note AND8003/D Application Note AND8002/D. Flammability Rating: UL 94 V0 0.125 in, Oxygen Index: 28 to 34 ORDERING INFORMATION Transistor Count = 73 devices Device Package Shipping These Devices are Pb-Free, Halogen Free and are RoHS Compliant MC10EL51DG SOIC8 98 Units/Tube (Pb-Free) MC10EL51DR2G SOIC8 2500/Tape & Reel (Pb-Free) MC10EL51DTG TSSOP8 100 Units/Tube (Pb-Free) MC100EL51DG SOIC8 98 Units/Tube (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC10EL51/DMC10EL51, MC100EL51 Table 1. TRUTH TABLE D* R* CLK* Q** R 1 8 V CC L L L Z H H L Z L X H X R Z = LOW to HIGH Transition D 2 D 7 Q * Pin will default low when left open. **Pin will default low when inputs are left open. Table 2. PIN DESCRIPTION CLK 3 6 Q PIN FUNCTION R ECL Reset Input D ECL Data Input CLK45 V EE CLK, CLK ECL Clock Inputs Q, Q ECL Data Outputs V Positive Supply Figure 1. Logic Diagram and Pinout Assignment CC V Negative Supply EE Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8NB 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8NB 41 to 44 C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) <2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power) www.onsemi.com 2