MC10H123 Triple 433Input Bus Driver Description The MC10H123 is a triple 4-3-3-Input Bus Driver. The MC10H123 consists of three NOR gates designed for bus driving applications on card or between cards. Output low logic levels www.onsemi.com are specified with V = 2.1 Vdc so that the bus may be terminated to OL 2.0 Vdc. The gate output, when low, appears as a high impedance to the bus, because the output emitter-followers of the MC10H123 are turned-off. This eliminates discontinuities in the characteristic impedance of the bus. 16 20 1 The V level is specified when driving a 25 load terminated to OH 1 2.0 Vdc, the equivalent of a 50 bus terminated at both ends. Although 25 is the lowest characteristic impedance that can be PDIP16 PLLC20 driven by the MC10H123, higher impedance values may be used with P SUFFIX FN SUFFIX CASE 64808 CASE 77502 this part. A typical 50 bus is shown in Figure 3. Features MARKING DIAGRAMS* Propagation Delay, 1.5 ns Typical Improved Noise Margin 150 mV 120 (Over Operating Voltage and Temperature Range) 16 Voltage Compensated MC10H123P 10H123G MECL 10K Compatible AWLYYWWG AWLYYWW These Devices are Pb-Free, Halogen Free and are RoHS Compliant 1 PDIP16 PLLC20 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping PLLC20 46 Units / Tube MC10H123FNG (Pb-Free) MC10H123FNR2G PLLC20 500 Tape & Reel (Pb-Free) 25 Units / Tube MC10H123PG PDIP16 (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: August, 2016 Rev. 8 MC10H123/DMC10H123 4 V V 1 16 5 CC1 CC2 3 6 C B 2 15 OUT OUT 7 A 3 14 C IN OUT 9 A C 4 13 IN IN 10 2 A C 5 12 IN IN V = PIN 1 CC1 11 V = PIN 16 CC2 A 6 11 B IN IN V = PIN 8 EE 12 A B 7 10 IN IN 13 15 V B 8 9 EE IN 14 Pin assignment is for Dual-in-Line Package. Figure 1. LOGIC DIAGRAM Figure 2. Dip Pin Assignment Table 1. MAXIMUM RATINGS Symbol Characteristic Rating Unit V Power Supply (V = 0) 8.0 to 0 Vdc EE CC V Input Voltage (V = 0) 0 to V Vdc I CC EE I Output Current mA out Continuous 50 Surge 100 T Operating Temperature Range 0 to +75 C A T Storage Temperature Range C stg Plastic 55 to +150 C Ceramic 55 to +165 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 2. ELECTRICAL CHARACTERISTICS (V = 5.2 V 5%) (Note 1) EE 0 25 75 Symbol Characteristic Min Max Min Max Min Max Unit I Power Supply Current 60 56 60 mA E I Input Current High 495 310 310 A inH I Input Current Low 0.5 0.5 0.3 A inL V High Output Voltage 1.02 0.84 0.98 0.81 0.92 0.735 Vdc OH V Low Output Voltage 2.1 2.03 2.1 2.03 2.1 2.03 Vdc OL V High Input Voltage 1.17 0.84 1.13 0.81 1.07 0.735 Vdc IH V Low Input Voltage 1.95 1.48 1.95 1.48 1.95 1.45 Vdc IL 1. Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Outputs are terminated through a 50 resistor to 2.1 V. www.onsemi.com 2