MC10H640 68030/040 PECL to TTL Clock Driver Description The MC10H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock www.onsemi.com specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its PLLC28 superior skew characteristic. FN SUFFIX The H640 includes divide-by-two and divide-by-four stages, both to CASE 77602 achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Diagram). MARKING DIAGRAM* Features Generates Clocks for 68030/040 1 Meets 030/040 Skew Requirements TTL or PECL Input Clock MC10H640G Extra TTL and PECL Power/Ground Pins AWLYYWW Asynchronous Reset Single +5.0 V Supply This Device is Pb-Free, Halogen Free and is RoHS Compliant A = Assembly Location Function WL = Wafer Lot YY = Year Reset (R): LOW on RESET forces all Q outputs LOW and all Q WW = Work Week outputs HIGH. G = Pb-Free Package Power-Up: The device is designed to have the POS edges of the 2 and 4 outputs synchronized at power up. *For additional marking information, refer to Application Note AND8002/D. Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this case, the ORDERING INFORMATION DE side of the input is pulled LOW, and DE goes HIGH. Device Package Shipping MC10H640FNG PLLC28 37 Units / Tube (Pb-Free) Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: August, 2016 Rev. 9 MC10H640/DMC10H640 TTL Outputs VT VT Q1 GT GT Q0 VT Q0 25 24 23 22 21 20 19 18 Q1 Q2 26 V BB TTL/ECL Clock Inputs GT 27 17 DE V Q2 BB 16 GT 28 DE DE Q3 2 MUX DE 15 VE Q3 1 DT Q0 VT 2 14 R SEL Q1 VT 3 13 GE Q0 4 12 DT 4 Q4 56 789 10 11 TTL Control Inputs Q1 Q5 GT GT Q4 Q5 VT SEL R Figure 1. Pinout: PLCC28 Figure 2. Logic Diagram (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION GT TTL Ground (0 V) VT TTL V (+5.0 V) CC VE ECL V (+5.0 V) CC GE ECL Ground (0 V) DE, DE ECL Signal Input (positive ECL) V V Reference Output BB BB DT TTL Signal Input Qn, Qn Signal Outputs (TTL) SEL Input Select (TTL) R Reset (TTL) Table 2. DC CHARACTERISTICS (V = V = 5.0 V 5%) T E 0C 25C 85C Min Max Min Max Min Max Unit Symbol Characteristic Condition I ECL VE Pin 57 57 57 mA Power Supply Current EE I TTL Total all VT pins 30 30 30 mA CCH I 30 30 30 mA CCL NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. www.onsemi.com 2