MC14070B, MC14077B CMOS SSI Quad Exclusive OR and NOR Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS Pchannel and N channel enhancement mode devices in a single monolithic MC14070B, MC14077B PIN ASSIGNMENT IN 1 1 14 V A DD IN 2 2 13 IN 2 A D OUT 3 12 IN 1 A D OUT 4 11 OUT B D IN 1 5 10 OUT B C IN 2 6 9 IN 2 B C V 7 8 IN 1 SS C MC14070B MC14077B QUAD Exclusive OR QUAD Exclusive NOR Gate Gate 1 1 3 3 2 2 5 5 4 4 6 6 8 8 10 10 9 9 12 12 11 11 13 13 V = PIN 14 DD V = PIN 7 SS (BOTH DEVICES) 20 ns 20 ns V V DD DD 90% 50% 10% V V in I SS DD 1/f V in * 50% DUTY CYCLE C L *Inverted output on MC14077B only. Figure 1. Power Dissipation Test Circuit and Waveform 20 ns 20 ns V DD V DD 90% PULSE INPUT 50% * GENERATOR 10% V SS t t PHL PLH C L V OH 90% V SS OUTPUT 50% 10% V OL t t THL TLH *Inverted output on MC14077B only. Connect unused input to V for MC14070B, to V for MC14077B. DD SS Figure 2. Switching Time Test Circuit and Waveforms