MC74AC253, MC74ACT253 Dual 4-Input Multiplexer with 3-State Outputs The MC74AC253/74ACT253 is a dual 4input multiplexer with 3state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a www.onsemi.com high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems. MARKING DIAGRAMS Multifunctional Capability 16 Noninverting 3State Outputs SOIC16 xxx253G Outputs Source/Sink 24 mA D SUFFIX 16 AWLYWW CASE 751B ACT253 Has TTL Compatible Inputs 1 1 These are PbFree Devices 16 V OE S I I I I Z xxx CC b 0 3b 2b 1b 0b b TSSOP16 253 16 16 15 14 13 12 11 10 9 DT SUFFIX ALYW CASE 948F 1 1 xxx = AC or ACT A = Assembly Location WL or L = Wafer Lot Y = Year 1 2 3 456 7 8 WW or W = Work Week OE S I I I I Z GND a 1 3a 2a 1a 0a a G or = PbFree Package Figure 1. Pinout: 16Lead Packages Conductors (Note: Microdot may be in either location) (Top View) PIN NAME ORDERING INFORMATION See detailed ordering and shipping information in the package PIN FUNCTION dimensions section on page 7 of this data sheet. I I Side A Data Inputs 0a 3a I I Side B Data Inputs 0b 3b S , S Common Select Inputs 0 1 OE Side A Output Enable Input a OE Side B Output Enable Input b Z Z 3State Outputs a, b Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: March, 2015 Rev. 7 MC74AC253/DMC74AC253, MC74ACT253 TRUTH TABLE Select Output Data Inputs Outputs Inputs Enable S S I I I I OE Z 0 1 0 1 2 3 OE I I I I I I I I OE a 0a 1a 2a 3a 0b 1b 2b 3b b X X X X X X H Z S 0 L L L X X X L L S 1 L L H X X X L H Z Z a b H L X L X X L L H L X H X X L H L H X X L X L L L H X X H X L H Figure 2. Logic Symbol H H X X X L L L H H X X X H L H Address inputs S and S are common to both sections. 0 1 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance FUNCTIONAL DESCRIPTION supplied to the two select inputs. The logic equations for the outputs are shown: The MC74AC253/74ACT253 contains two identical 4input multiplexers with 3state outputs. They select two Z = OE (I S S +I S S + a a 0a 1 0 1a 1 0 I S S +I S S ) bits from four sources selected by common Select inputs (S , 2a 1 0 3a 1 0 0 Z = OE (I S S +I S S + b b 0b 1 0 1b 1 0 S ). The 4input multiplexers have individual Output 1 I S S +I S S ) 2b 1 0 3b 1 0 Enable (OE , OE ) inputs which, when HIGH, force the a b If the outputs of 3state devices are tied together, all but outputs to a high impedance (High Z) state. This device is the one device must be in the high impedance state to avoid high logic implementation of a 2pole, 4position switch, where currents that would exceed the maximum ratings. Designers the position of the switch is determined by the logic levels should ensure that Output Enable signals to 3state devices whose outputs are tied together are designed so that there is no overlap. OE I I I I S S I I I I OE b 3b 2b 1b 0b 0 1 3a 2a 1a 0a a Z Z b a NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2