MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
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the Clock Enable (CE) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flops Q
output. The CE input must be stable only one setup time prior to the
SOIC20W
DW SUFFIX
LOW-to-HIGH clock transition for predictable operation.
CASE 751D
1
Features
Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
TSSOP20
Eight Edge-Triggered D Flip-Flops
DT SUFFIX
Buffered Common Clock
CASE 948E
Outputs Source/Sink 24 mA
1
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
ORDERING INFORMATION
See MC74AC374 for 3-State Version
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ACT377 Has TTL Compatible Inputs
MSL = 1 for all Surface Mount
DEVICE MARKING INFORMATION
Chip Complexity: 292 FETs or 73 Gates
See general marking information in the device marking
section on page 7 of this data sheet.
These are PbFree Devices
V O D D O O D D O CP
CC 7 7 6 6 5 5 4 4
20 19 18 17 16 15 14 13 12 11
1 2 345 67 8 9 10
CE O D D O O D D O GND
0 0 1 1 2 2 3 3
Figure 1. Pinout: 20Lead Packages Conductors
(Top View)
PIN NAMES
D D D D D D D D
0 1 2 3 4 5 6 7
PIN FUNCTION
CP
D D Data Inputs
0 7 CE
O O O O O O O O
CE Clock Enable (Active LOW)
0 1 2 3 4 5 6 7
Q Q Data Outputs
0 7
CP Clock Pulse Input
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2015
1 Publication Order Number:
March, 2015 Rev. 10 MC74AC377/DMC74AC377, MC74ACT377
MODE SELECT-FUNCTION TABLE
Inputs Outputs
Operating Mode
CP CE D Q
n n
Load 1 L H H
Load 0 L L L
H X No Change
Hold (Do Nothing)
X H X No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
D D D D D D D D
0 1 2 3 4 5 6 7
CE
DQ DQ DQ DQ DQ DQ DQ DQ
CP CP CP CP CP CP CP CP
CP
O O O O O O O O
0 1 2 3 4 5 6 7
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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2