MC74ACT138DTR2G

MC74AC138, MC74ACT138 1-of-8 Decoder/Demultiplexer The MC74AC138/74ACT138 is a highspeed 1of8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. www.onsemi.com The multiple input enables allow parallel expansion to a 1of24 decoder using just three MC74AC138/74ACT138 devices or a MARKING 1of32 decoder using four MC74AC138/74ACT138 devices and one DIAGRAMS inverter. 16 Demultiplexing Capability SOIC16 xxx138G D SUFFIX Multiple Input Enable for Easy Expansion 16 AWLYWW CASE 751B Active LOW Mutually Exclusive Outputs 1 1 Outputs Source/Sink 24 mA 16 ACT138 Has TTL Compatible Inputs xxx These are PbFree Devices TSSOP16 138 16 DT SUFFIX ALYW CASE 948F 1 V O O O O O O O CC 0 1 2 3 4 5 6 1 16 15 14 13 12 11 10 9 xxx = AC or ACT A = Assembly Location WL or L = Wafer Lot Y = Year WW or W = Work Week G or = PbFree Package (Note: Microdot may be in either location) 1 2 3 4 567 8 A A A E E E O GND 0 1 2 1 2 3 7 Figure 1. Pinout: 16Lead Packages Conductors (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. A A A E E E 0 1 2 1 2 3 O O O O O O O O 0 1 2 3 4 5 6 7 Figure 2. Logic Symbol PIN ASSIGNMENT PIN FUNCTION A A Address Inputs 0 2 E E Enable Inputs 1 2 E Enable Input 3 O O Outputs 0 7 Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: January, 2015 Rev. 7 MC74AC138/DMC74AC138, MC74ACT138 FUNCTIONAL DESCRIPTION HIGH. This multiple enabled function allows easy parallel expansion of the device to a 1of32 (5 lines to 32 lines) The MC74AC138/74ACT138 highspeed 1of8 decoder with just four MC74AC138/74ACT138 devices decoder/demultiplexer accepts three binary weighted inputs and one inverter (See Figure 4). The (A , A , A ) and, when enabled, provides eight mutually 0 1 2 MC74AC138/74ACT138 can be used as an 8output exclusive activeLOW outputs (O O). The 0 7 demultiplexer by using one of the active LOW Enable inputs MC74AC138/74ACT138 features three Enable inputs, two as the data input and the other Enable inputs as strobes. The activeLOW (E , E ) and one activeHIGH (E ). All 1 2 3 Enable inputs which are not used must be permanently tied outputs will be HIGH unless E and E are LOW and E is 1 2 3 to their appropriate activeHIGH or activeLOW state. TRUTH TABLE Inputs Outputs E E E A A A O O O O O O O O 1 2 3 0 1 2 0 1 2 3 4 5 6 7 H X X X X X H H H H H H H H X H X X X X H H H H H H H H X X L X X X H H H H H H H H L L H L L L L H H H H H H H L L H H L L H L H H H H H H L L H L H L H H L H H H H H L L H H H L H H H L H H H H L L H L L H H H H H L H H H L L H H L H H H H H H L H H L L H L H H H H H H H H L H L L H H H H H H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial E E E 1 2 3 A A A 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2