MC74ACT573DWG ON Semiconductor

MC74AC573, MC74ACT573 Octal Buffer/Line Driver with 3-State Outputs The MC74AC573/74ACT573 is a highspeed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. www.onsemi.com The MC74AC573/74ACT573 is functionally identical to the MC74AC373/74ACT373 but has inputs and outputs on opposite sides. MARKING Features DIAGRAM Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors Useful as Input or Output Port for Microprocessors 20 xxx573 1 Functionally Identical to MC74AC373/74ACT373 AWLYYWWG SO20 3State Outputs for Bus Interfacing DW SUFFIX Outputs Source/Sink 24 mA CASE 751D ACT573 Has TTL Compatible Inputs These are PbFree Devices V O O O O O O O O LE CC 0 1 2 3 4 5 6 7 20 xxx 1 573 20 19 18 17 16 15 14 13 12 11 ALYW TSSOP20 DT SUFFIX CASE 948E xxx = AC or ACT A = Assembly Location WL, L = Wafer Lot 1 2 3456 7 9 8 10 YY, Y = Year OE D D D D D D D D GND WW, W = Work Week 0 1 2 3 4 5 6 7 G or = PbFree Package Figure 1. Pinout 20Lead Packages Conductors (Note: Microdot may be in either location) (Top View) PIN ASSIGNMENT ORDERING INFORMATION See detailed ordering and shipping information in the package PIN FUNCTION dimensions section on page 8 of this data sheet. D D Data Inputs 0 7 LE Latch Enable Input OE 3State Output Enable Input O O 3State Latch Outputs 0 7 D D D D D D D D 0 1 2 3 4 5 6 7 LE OE O O O O O O O O 0 1 2 3 4 5 6 7 Figure 2. Logic Symbol Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: March, 2015 Rev. 8 MC74AC573/DMC74AC573, MC74ACT573 Functional Description TRUTH TABLE The MC74AC573/74ACT574 contains eight Dtype Inputs Outputs latches with 3state output buffers. When the Latch Enable OE LE D O (LE) input is HIGH, data on the D inputs enters the latches. n n n In this condition the latches are transparent, i.e., a latch L H H H output will change state each time its D input changes. When L H L L LE is LOW the latches store the information that was present L L X O 0 on the D inputs a setup time preceding the HIGHtoLOW transition of LE. The 3state buffers are controlled by the H X X Z Output Enable (OE) input. When OE is LOW, the buffers are H = HIGH Voltage Level enabled. When OE is HIGH the buffers are in the high L = LOW Voltage Level Z = High Impedance impedance mode but this does not interfere with entering X = Immaterial new data into the latches. O = Previous O before LOWtoHIGH Transition of Clock 0 0 D D D D D D D D 0 1 2 3 4 5 6 7 D D D D D D D D Q Q Q Q Q Q Q Q LE LE LE LE LE LE LE LE LE OE O O O O O O O O 0 1 2 3 4 5 6 7 NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram www.onsemi.com 2