MC74LCX240 Low-Voltage CMOS Octal Buffer With 5 VTolerant Inputs and Outputs (3State, Inverting) www.onsemi.com The MC74LCX240 is a high performance, inverting octal buffer operating from a 2.3 to 3.6 V supply. High impedance TTL compatible MARKING inputs significantly reduce current loading to input drivers while TTL DIAGRAMS compatible outputs offer improved switching noise performance. A V I 20 specification of 5.5 V allows MC74LCX240 inputs to be safely driven 20 from 5 V devices. The MC74LCX240 is suitable for memory address LCX240 driving and all TTL level bus oriented transceiver applications. AWLYYWWG 1 Current drive capability is 24 mA at the outputs. The Output Enable SOIC20 WB (OE) input, when HIGH, disables the outputs by placing them in DW SUFFIX 1 a HIGH Z condition. CASE 751D Features Designed for 2.3 to 3.6 V V Operation CC 20 20 5 V Tolerant Interface Capability With 5 V TTL Logic LCX 1 Supports Live Insertion and Withdrawal 240 ALYW TSSOP20 I Specification Guarantees High Impedance When V = 0 V OFF CC DT SUFFIX LVTTL Compatible CASE 948E 1 LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability A = Assembly Location Near Zero Static Supply Current in All Three Logic States (10 A) WL, L = Wafer Lot Substantially Reduces System Power Requirements YY, Y = Year Latchup Performance Exceeds 500 mA WW, W = Work Week G or = PbFree Package ESD Performance: Human Body Model >2000 V (Note: Microdot may be in either location) Machine Model >200 V These Devices are PbFree, Halogen Free/BFR Free and are RoHS ORDERING INFORMATION Compliant See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: March, 2019 Rev. 11 MC74LCX240/DMC74LCX240 1 1OE V 2OE 1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3 CC 2 18 1D0 1O0 20 19 18 17 16 15 14 13 12 11 4 16 1D1 1O1 6 14 1D2 1O2 1 2 34567 9 8 10 8 12 1D3 1O3 1OE 1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND Figure 1. Pinout: 20Lead (Top View) 19 2OE 17 3 2D0 2O0 15 5 PIN NAMES 2D1 2O1 Pins Function 13 7 nOE Output Enable Inputs 2D2 2O2 1Dn, 2Dn Data Inputs 11 9 1On, 2On 3State Outputs 2D3 2O3 Figure 2. LOGIC DIAGRAM TRUTH TABLE INPUTS OUTPUTS 1OE 1Dn 2OE 2Dn 1On, 2On L L H L H L H X Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions Are Acceptable for I reasons, DO NOT FLOAT Inputs CC www.onsemi.com 2