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This literature is subject to all applicable copyright laws and is not for resale in any manner.MM74HC138 3-to-8 Line Decoder September 1983 Revised February 1999 MM74HC138 3-to-8 Line Decoder The decoders outputs can drive 10 low power Schottky General Description TTL equivalent loads, and are functionally and pin equiva- The MM74HC138 decoder utilizes advanced silicon-gate lent to the 74LS138. All inputs are protected from damage CMOS technology and is well suited to memory address due to static discharge by diodes to V and ground. CC decoding or data routing applications. The circuit features high noise immunity and low power consumption usually Features associated with CMOS circuitry, yet has speeds compara- ble to low power Schottky TTL logic. Typical propagation delay: 20 ns The MM74HC138 has 3 binary select inputs (A, B, and C). Wide power supply range: 2V6V If the device is enabled, these inputs determine which one Low quiescent current: 80 A maximum (74HC Series) of the eight normally HIGH outputs will go LOW. Two active Low input current: 1 A maximum LOW and one active HIGH enables (G1, G2A and G2B) Fanout of 10 LS-TTL loads are provided to ease the cascading of decoders. Ordering Code: Order Number Package Number Package Description MM74HC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Pin Assignment for DIP, SOIC, SOP and TSSOP 1999 Fairchild Semiconductor Corporation DS005120.prf www.fairchildsemi.com