MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder
September 1983
Revised February 1999
MM74HC259
8-Bit Addressable Latch/3-to-8 Line Decoder
inputs. To eliminate the possibility of entering erroneous
General Description
data into the latches, the enable should be held HIGH
The MM74HC259 device utilizes advanced silicon-gate
(inactive) while the address lines are changing.
CMOS technology to implement an 8-bit addressable latch,
If enable is held HIGH and CLEAR is taken LOW all eight
designed for general purpose storage applications in digital
latches are cleared to a LOW state. If enable is LOW all
systems.
latches except the addressed latch will be cleared. The
The MM74HC259 has a single data input (D), 8 latch out-
addressed latch will instead follow the D input, effectively
puts (Q1Q8), 3 address inputs (A, B, and C), a common
implementing a 3-to-8 line decoder.
enable input (G), and a common CLEAR input. To operate
All inputs are protected from damage due to static dis-
this device as an addressable latch, data is held on the D
charge by diodes to V and ground.
CC
input, and the address of the latch into which the data is to
be entered is held on the A, B, and C inputs. When
Features
ENABLE is taken LOW the data flows through to the
addressed output. The data is stored when ENABLE transi-
Typical propagation delay: 18 ns
tions from LOW-to-HIGH. All unaddressed latches will
Wide supply range: 26V
remain unaffected. With enable in the HIGH state the
Low input current: 1 A maximum
device is deselected, and all latches remain in their previ-
ous state, unaffected by changes on the data or address
Low quiescent current: 80 A maximum (74HC Series)
Ordering Code:
Order Number Package Number Package Description
MM74HC259M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
MM74HC259SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC259MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC259N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Connection Diagram Latch Selection Table
Pin Assignments for DIP, SOIC, SOP and TSSOP Select Inputs Latch
C B A Addressed
LLL 0
LL H 1
LH L 2
LH H 3
HL L 4
HL H 5
HH L 6
HHH 7
H = HIGH level, L = LOW level
D = the level at the data input
Q the level of Q (i = 0, 1...7, as appropriate)
i0 i
Top View
before the indicated steady-state input
conditions were established.
1999 Fairchild Semiconductor Corporation DS005006.prf www.fairchildsemi.comTruth Table
Inputs Outputs of Each
Addressed Other Function
Clear G Latch Output
HL D Q Addressable Latch
i0
HH Q Q Memory
i0 i0
L L D L 8-Line Decoder
L H L L Clear
Logic Diagram
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MM74HC259