MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop February 1990 Revised May 2005 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description Features The MM74HCT573 octal D-type latches and TTL input characteristic compatible MM74HCT574 octal D-type flip-flop advanced silicon-gate Typical propagation delay: 18 ns CMOS technology, which provides the inherent benefits of Low input current: 1 PA maximum low power consumption and wide power supply range, but Low quiescent current: 80 PA maximum are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 Compatible with bus-oriented systems LS-TTL loads. All inputs are protected from damage due to Output drive capability: 15 LS-TTL loads static discharge by internal diodes to V and ground. CC When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the out- puts until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Ordering Codes: Order Number Package Number Package Description MM74HCT573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HCT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide MM74HCT574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide MM74HCT574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT574N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. 2005 Fairchild Semiconductor Corporation DS010627 www.fairchildsemi.comConnection Diagrams Truth Tables MM74HCT573 Output LE Data Output Control L HHH LH L L LL X Q 0 HX X Z H HIGH Level L LOW Level Q Level of output before steady-state input conditions were established. 0 Z High Impedance State Top View MM74HCT573 MM74HCT574 Output LE Data Output Control L n HH L n LL LL X Q 0 HX X Z H HIGH Level L LOW Level Q Level of output before steady-state input conditions were established. 0 X Dont Care Z High Impedance State n Transition from LOW-to-HIGH Top View MM74HCT574 www.fairchildsemi.com 2 MM74HCT573 MM74HCT574