NB100LVEP56DTR2G

NB100LVEP56 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer Description The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low www.onsemi.com skew clock or differential data signals. The device features both individual and common select inputs to address both data path and MARKING random logic applications. Common and individual selects can accept DIAGRAMS* both LVECL and LVCMOS input voltage levels. Multiple V pins BB are provided. N100 The V pin, an internally generated voltage supply, is available to BB VP56 this device only. For singleended input operation, the unused ALYW TSSOP20 WB differential input is connected to V as a switching reference voltage. BB DT SUFFIX V may also rebias AC coupled inputs. When used, decouple V BB BB CASE 948E and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB 24 1 N100 Features 24 1 VP56 Maximum Input Clock Frequency > 2.5 GHz Typical ALYW QFN24 Maximum Input Data Rate > 2.5 Gb/s Typical MN SUFFIX CASE 485L 525 ps Typical Propagation Delays Low Profile QFN Package A = Assembly Location L = Wafer Lot PECL Mode Operating Range: Y = Year V = 2.375 V to 3.8 V with V = 0 V CC EE W = Work Week NECL Mode Operating Range: = PbFree Package V = 0 V with V = 2.375 V to 3.8 V CC EE (Note: Microdot may be in either location) Separate, Common Select, and Individual Select *For additional marking information, refer to Application Note AND8002/D. (Compatible with ECL and CMOS Input Voltage Levels) Q Output Will Default LOW with Inputs Open or at V EE Multiple V Outputs BB ORDERING INFORMATION These Devices are PbFree and are RoHS Compliant See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: February, 2016 Rev. 11 NB100LVEP56/DNB100LVEP56 Table 1. PIN FUNCTION DESCRIPTION Pin No. Default TSSOP QFN State Name I/O Description 14,20 3,9,18,19, V Positive Supply Voltage. All VCC Pins must be Externally CC 20 Connected to Power Supply to Guarantee Proper Operation. 11 15,24 V Negative Supply Voltage. All VEE Pins must be Externally EE Connected to Power Supply to Guarantee Proper Operation. 3,8 6,12 V , ECL Reference Voltage Output BB0 V BB1 1 4 D0a ECL Input Low Noninverted Differential Data a Input to MUX 0. Internal 75 k to V . EE 2 5 D0a ECL Input High Inverted Differential Data a Input to MUX 0. Internal 75 k to V EE and 37 k to V . CC 4 7 D0b ECL Input Low Noninverted Differential Data b Input to MUX 0. Internal 75 k to V . EE 5 8 D0b ECL Input High Inverted Differential Data b Input to MUX 0. Internal 75 k to V EE and 37 k to V . CC 6 10 D1a ECL Input Low Noninverted Differential Data a Input to MUX 1. Internal 75 k to V . EE 7 11 D1a ECL Input High Inverted Differential Data a Input to MUX 1. Internal 75 k to V EE and 37 k to V . CC 9 13 D1b ECL Input Low Noninverted Differential Data b Input to MUX 1. Internal 75 k to V . EE 10 14 D1b ECL Input High Inverted Differential Data b Input to MUX 1. Internal 75 k to V EE and 37 k to V . CC 19 2 Q0 ECL Output Noninverted Differential Output MUX 0. Typically Terminated with 50 to V = V 2.0 V. TT CC 18 1 Q0 ECL Output Inverted Differential Output MUX 0. Typically Terminated with 50 to V = V 2.0 V. TT CC 13 17 Q1 ECL Output Noninverted Differential Output MUX 1. Typically Terminated with 50 to V = V 2.0 V. TT CC 12 16 Q1 ECL Output Inverted Differential Output MUX 1. Typically Terminated with 50 to V = V 2.0 V. TT CC 17 23 SEL0 ECL, CMOS Low Noninverted Differential Select Input to MUX 0. Internal 75 k to Input V . EE 16 22 COM SEL ECL, CMOS Low Noninverted Differential Common Select Input to Both MUX. Input Internal 75 k to V . EE 15 21 SEL1 ECL, CMOS Low Noninverted Differential Select Input to MUX 1. Internal 75 k to Input V . EE N/A EP Exposed Pad. The exposed pad (EP) on the package bottom must be attached to a heatsinking conduit. The exposed pad may only be electrically connected to V . EE www.onsemi.com 2