NB3N2304NZDTR2G ON Semiconductor

NB3N2304NZ 3.3V 1:4 Clock Fanout Buffer Description The NB3N2304NZ is a low skew 1to 4 clock fanout buffer, designed for high speed clock distribution such as in PCI X NB3N2304NZ Logic OE Control IN Q4 1 8 Q1 2 7 OE Q3 Q2 3 6 Q1 V DD IN Q3 4 5 GND Q2 Q4 Figure 2. Block Diagram Figure 3. NB3N2304NZ Package Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name Pin Type Description 1 IN LVCMOS/LVTTL Input Clock Input 2 OE LVCMOS/LVTTL Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs are forced to logic LOW when OE is forced LOW. 3 Q1 LVCMOS/LVTTL Output Clock Output 1 4 GND Power Negative Supply Voltage Connect to Ground, 0 V 5 Q2 (LV)CMOS/(LV)TTL Input Clock Output 2 6 V Power Positive Supply Voltage (3.0 V to 3.6 V) DD 7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3 8 Q4 (LV)CMOS/(LV)TTL Input Clock Output 4 EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. OE, OUTPUT ENABLE FUNCTION TABLE Inputs Outputs IN OE L L L H L L L H L H H H