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NB4L16M 2.5 V/3.3 V, 5 Gb/s Multi Level Clock/Data Input to CML Driver/Receiver/Buffer/ Translator with Internal www.onsemi.com Termination Description The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, HSTL, LVCMOS/LVTTL 1 and produce 400 mV CML output. The device is capable of receiving, QFN16 buffering, and translating a clock or data signal that is as small as MN SUFFIX 75 mV operating up to 3.5 GHz or 5.0 Gb/s, respectively. As such, it is CASE 485G01 ideal for SONET, GigE, Fiber Channel and backplane applications (see Table 6 and Figures 20, 21 22, and 23). Differential inputs incorporate internal 50 termination resistors MARKING DIAGRAM* and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, HSTL or LVDS. The differential 16 mA CML output provides matching 16 internal 50 termination, and 400 mV output swing when externally 1 receiver terminated, 50 to V (see Figure 19). These features CC NB4L 16M provide transmission line termination on chip, at the receiver and ALYW driver end, eliminating any use of additional external components. The V , an internally generated voltage supply, is available to this BB device only. For single-ended input configuration, the unused A = Assembly Location complementary differential input is connected to V as a switching BB L = Wafer Lot reference voltage. The V reference output can be used also to BB Y = Year re-bias capacitor coupled differential or single-ended output signals. W = Work Week For the capacitor coupled input signals, V should be connected to BB = Pb-Free Package the V pin and bypassed to ground with a 0.01 F capacitor. When TD (Note: Microdot may be in either location) not used V should be left open. BB This device is housed in a 3x3 mm 16 pin QFN package. *For additional marking information, refer to Application notes, models, and support documentation are available at Application Note AND8002/D. www.onsemi.com. Features ORDERING INFORMATION Maximum Input Clock Frequency up to 3.5 GHz Device Package Shipping Maximum Input Data Rate up to 5.0 Gb/s NB4L16MMNG QFN16 123 Units/Tube < 0.7 ps Maximum Clock RMS Jitter (Pb-Free) < 10 ps Maximum Data Dependent Jitter at 2.5 Gb/s NB4L16MMNR2G QFN16 3000/Tape & Reel 220 ps Typical Propagation Delay (Pb-Free) 60 ps Typical Rise and Fall Times For information on tape and reel specifications, in- CML Output with Operating Range: cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications V = 2.375 V to 3.6 V with V = 0 V CC EE Brochure, BRD8011/D. CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices These Devices are Pb-Free, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: October, 2018 Rev. 5 NB4L16M/D