3.3 V Differential 1:21 Differential Fanout Clock Driver with HCSL level Output NB4N121K www.onsemi.com Description The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low QFN52 propagation delay variation. The NB4N121K is designed with HCSL MN SUFFIX clock distribution for FBDIMM applications in mind. CASE 485M Inputs can accept differential LVPECL, CML, or LVDS levels. 152 Singleended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper V supply (see Figures 5, 10, 11, 12, REFAC and 13). Clock input pins incorporate an internal 50 on die MARKING DIAGRAM* termination resistors. 52 Output drive current at I (Pin 1) for 1X load is selected by REF 1 connecting to GND. To drive a 2X load, connect I to V . See REF CC Figure 9. NB4N 121K The NB4N121K specifically guarantees low outputtooutput AWLYYWWG skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N121Ks performance to distribute low skew A = Assembly Site clocks across the backplane or the motherboard. WL = Wafer Lot YY = Year Features WW = Work Week Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and G = PbFree Package 400 MHz *For additional marking information, refer to 340 ps Typical Rise and Fall Times Application Note AND8002/D. 800 ps Typical Propagation Delay tpd 100 ps Maximum Propagation Delay Variation Per Each Q0 Differential Pair Q0 Additive Phase RMS Jitter: 1 ps Max VTCLK Operating Range: V = 3.0 V to 3.6 V with V = 0 V Q1 CC EE Differential HCSL Output Level (700 mV PeaktoPeak) Q1 These Devices are PbFree, Halogen Free/BFR Free and are RoHS CLK Compliant CLK Q19 Q19 VTCLK Q20 V CC Q20 I REF R REF GND Figure 1. Pin Configuration (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2021 Rev. 7 NB4N121K/DNB4N121K Exposed Pad (EP) VCC 39 I 1 REF GND 2 38 Q6 Q6 VTCLK 3 37 CLK 36 Q7 4 Q7 CLK 5 35 VTCLK 6 34 Q8 V 7 NB4N121K 33 Q8 CC Q20 8 32 Q9 9 31 Q9 Q20 Q19 10 30 Q10 Q19 11 29 Q10 12 Q11 Q18 28 13 27 Q11 Q18 Figure 2. Pinout Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 I Output Output current programming pin to select load drive. For 1X REF configuration, connect I to GND, or for 2X configuration, connect REF I to V (See Figure 9). REF CC 2 GND Supply Ground. GND pin must be externally connected to power supply to guarantee proper operation. 3, 6 VTCLK, Internal 50 Termination Resistor connection Pins. In the differential VTCLK configuration when the input termination pins are connected to the com- mon termination voltage, and if no signal is applied then the device may be susceptible to selfoscillation. 4 CLK LVPECL Input CLOCK Input (TRUE) 5 CLK LVPECL Input CLOCK Input (INVERT) 7, 26, 39, 52 V Positive Supply pins. V pins must be externally connected to a power CC CC supply to guarantee proper operation. 8, 10, 12, 14, 16, 18, 20, 22, Q 200 HCSL Output Output (INVERT) 24, 27, 29, 31, 33, 35, 37, 40, 42, 44, 46, 48, 50 9, 11, 13, 15, 17, 19, 21, 23, Q 200 HCSL Output Output (TRUE) 25, 28, 30, 32, 34, 36, 38, 41, 43, 45, 47, 49, 51 Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heatsinking conduit for proper thermal operation. (Note 1) 1. The exposed pad must be connected to the circuit board ground. www.onsemi.com 2 Q17 52 VCC 14 Q0 Q17 15 51 Q0 Q16 16 50 Q1 49 Q16 17 Q15 Q1 18 48 Q15 19 47 Q2 46 Q2 Q14 20 Q3 Q14 21 45 Q3 Q13 22 44 Q4 Q13 23 43 Q12 24 42 Q4 Q5 Q12 25 41 VCC Q5 26 40