NB6L14MMNR2G ON Semiconductor

NB6L14M 2.5 V/3.3 V3.0 GHz Differential 1:4 CML Fanout Buffer Multi-Level Inputs with Internal Termination NB6L14M Q0 Q0 Q0 V GND CC /Q0 Exposed Pad (EP) 16 15 14 13 Q1 Q1 1 12 IN /Q1 IN 50 Q1 2 11 VT VT 50 IN Q2 3 10 V Q2 REFAC /Q2 Q2 4 9 IN D Q EN 56 7 8 CLK Q3 VREFAC Q3 Q3 V EN CC /Q3 Figure 2. QFN-16 Pinout Figure 3. Logic Diagram (Top View) Table 1. EN TRUTH TABLE IN IN EN Q0:Q3 Q0:Q3 0 1 1 0 1 1 0 1 1 0 x x 0 0+ 1+ + = On next negative transition of the input signal (IN). x = Don t care. Table 2. PIN DESCRIPTION Pin Name I/O Description 1 Q1 CML Output Non-inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 2 Q1 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 3 Q2 CML Output Non-inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 4 Q2 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 5 Q3 CML Output Non-inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 6 Q3 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC 7 V - Positive Supply Voltage CC 8 EN LVTTL/LVCMOS Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will go HIGH on the next negative transition of IN input. The internal D register is FF clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal pullup resistor and defaults HIGH when left open. 9 IN LVPECL, CML, Inverted Differential Clock Input. Internal 50 Resistor to Termination Pin, VT. LVDS 10 V Output Voltage Reference for capacitor-coupled inputs, only. REFAC 11 VT Internal 100 center-tapped Termination Pin for IN and IN. 12 IN LVPECL, CML, Non-inverted Differential Clock Input. Internal 50 Resistor to Termination Pin, VT. LVDS 13 GND - Negative Supply Voltage 14 V - Positive Supply Voltage CC 15 Q0 CML Output Noninverted Differential Output. Typically Terminated with 50 Resistor to V . CC 16 Q0 CML Output Inverted Differential Output. Typically Terminated with 50 Resistor to V . CC - EP - The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal is applied on IN/IN inputs, then the device will be susceptible to self-oscillation.