NB6N239S 3.3 V, 3.0 GHz Any Differential Clock IN to LVDS OUT 1/2/4/8, 2/4/8/16 Clock Divider NB6N239S MR SELA0 SELA1 V CC 16 15 14 13 1 12 QA VT 11 CLK 2 QA NB6N239S CLK 3 10 QB V 4 9 QB BBAC 5 678 EN SELB0 SELB1 GND Exposed Pad (EP) Figure 2. Pinout: QFN16 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VT Internal 100 CenterTapped Termination Pin for CLK and CLK. 2 CLK LVDS, LVPECL, CML, Noninverted Differential CLOCK Input. HCSL, HSTL Input 3 CLK LVDS, LVPECL, CML, Inverted Differential CLOCK Input. HCSL, HSTL Input 4 V Output Voltage Reference for Capacitor Coupled Inputs, only. BBAC 5 EN* LVCMOS/LVTTL Input Synchronous Output Enable 6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin 7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin 8 GND Power Supply Negative Supply Voltage 9 QB LVDS Output Inverted Differential Output. Typically terminated with 100 across differential outputs. 10 QB LVDS Output Noninverted Differential Output. Typically terminated with 100 across differential outputs. 11 QA LVDS Output Inverted Differential Output. Typically terminated with 100 across differential outputs. 12 QA LVDS Output Noninverted Differential Output. Typically terminated with 100 across differential out- puts. 13 V Power Supply Positive Supply Voltage. CC 14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin 15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin 16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW EP Power Supply (OPT) The Exposed Pad on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is electrically connected to the die, and is recommended to be electrically and thermally connected to GND on the PC board. *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.