1.8 V/2.5 V, 10 GHz 2 Clock Divider with CML Outputs MultiLevel Inputs w/ Internal Termination NB7V32M www.onsemi.com Description The NB7V32M is a differential 2 Clock divider with asynchronous reset. The differential Clock inputs incorporate internal 1 50 termination resistors and will accept LVPECL, CML and LVDS logic levels. QFN16 The NB7V32M produces a 2 output copy of an input Clock MN SUFFIX operating up to 10 GHz with minimal jitter. CASE 485G The RESET Pin is asserted on the rising edge. Upon powerup, the internal flipflops will attain a random state the Reset allows for the MARKING DIAGRAM* synchronization of multiple NB7V32Ms in a system. 16 The 16 mA differential CML output provides matching internal 1 50 termination which guarantees 400 mV output swing when NB7V externally receiver terminated with 50 to V . 32M CC ALYW The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M (2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16pin QFN package. The NB7V32M is a member of the GigaComm family of high performance clock products. Application notes, A = Assembly Location models, and support documentation are available at L = Wafer Lot Y = Year www.onsemi.com. W = Work Week = PbFree Package Features (Note: Microdot may be in either location) Maximum Input Clock Frequency > 10 GHz, typical *For additional marking information, refer to Random Clock Jitter < 0.8 ps RMS Application Note AND8002/D. 200 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times R Differential CML Outputs, 400 mV PeaktoPeak, Typical Operating Range: V = 1.71 V to 2.625 V with GND = 0 V CC Internal 50 Input Termination Resistors RESET QFN16 Package, 3 mm x 3 mm VTCLK 40C to +85C Ambient Operating Temperature 50 CLK These Devices are PbFree and RoHS Compliant Q 2 Q CLK 50 VTCLK VREFAC Figure 1. Simplified Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2010 1 Publication Order Number: May, 2021 Rev. 6 NB7V32M/DNB7V32M Exposed Pad (EP) VCC R VCC VCC Table 1. TRUTH TABLE 16 15 14 13 CLK CLK R Q Q x x H L H VTCLK 1 12 VCC Z W L CLK 2 CLK 2 CLK 2 11 Q Z = LOW to HIGH Transition NB7V32M W = HIGH to LOW Transition x = Dont Care CLK Q 3 10 VTCLK VCC 4 9 56 7 8 VREFAC GND GND GND Figure 2. Pin Configuration (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1 VTCLK Internal 50 Termination Pin for CLK 2 CLK LVPECL, CML, Noninverted Differential CLK Input. (Note 1) LVDS Input 3 CLK LVPECL, CML, Inverted Differential CLK Input. (Note 1) LVDS Input 4 VTCLK Internal 50 Termination Pin for CLK 5 VREFAC Internally Generated Output Voltage Reference for Capacitor Coupled Inputs, only 6 GND Negative Supply Voltage 7 GND Negative Supply Voltage 8 GND Negative Supply Voltage 9 VCC Positive Supply Voltage. (Note 2) 10 Q CML Output Inverted Differential Output 11 Q CML Output NonInverted Differential Output 12 VCC Positive Supply Voltage. (Note 2) 13 VCC Positive Supply Voltage. (Note 2) 14 VCC Positive Supply Voltage. (Note 2) 15 R LVCMOS Input Asynchronous Reset Input. Internal 75 k pulldown to GND. 16 VCC Positive Supply Voltage. (Note 2) EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 source termination resistors. 2. VCC and GND pins must be externally connected to a power supply for proper operation. www.onsemi.com 2