NB7V586M 1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer / Translator NB7V586M Table 1. INPUT SELECT FUNCTION TABLE Exposed Pad (EP) SEL* CLK Input Selected 0 IN0 32 31 30 29 28 27 26 25 1 IN1 IN0 1 24 GND *Defaults HIGH when left open. 2 23 VT0 VCC02 Q2 3 22 VREFAC0 4 21 Q2 IN0 NB7V586M 5 20 IN1 Q3 VT1 6 19 Q3 7 18 VCC02 VREFAC1 IN1 8 17 GND 9 10 11 12 13 14 15 16 Figure 1. 32 Lead QFN Pinout (Top View) Table 2. PIN DESCRIPTION Pin Name I/O Description 1,4 IN0, IN0 LVPECL, CML, Noninverted, Inverted, Differential Inputs 5,8 IN1, IN1 LVDS Input 2,6 VT0, VT1 Internal 100 Centertapped Termination Pin for IN0/IN0 and IN1/IN1 31 SEL LVTTL/LVCMOS Input Select pin LOW for IN0 Inputs, HIGH for IN1 Inputs defaults HIGH when left open Input 10 NC No Connect 30 VCC 1.8 V Positive Supply Voltage for the Inputs and Core Logic. 25 VCCO1 1.2 V or 1.8 V Positive Supply Voltage for the Q0, Q0, Q1, Q1 CML Outputs 18, 23 VCCO2 1.2 V or 1.8 V Positive Supply Voltage for the Q2, Q2, Q3, Q3 CML Outputs 11, 16 VCCO3 1.2 V or 1.8 V Positive Supply Voltage for the Q4, Q4, Q5, Q5 CML Outputs 29, 28 Q0, Q0 1.2 V or 1.8 V Noninverted, Inverted Differential Outputs powered by VCCO1 (Notes 1 and 2). 27, 26 Q1, Q1 CML Output 22, 21 Q2, Q2 1.2 V or 1.8 V Noninverted, Inverted Differential Outputs powered by VCCO2 (Notes 1 and 2). 20, 19 Q3, Q3 CML Output 15, 14 Q4, Q4 1.2 V or 1.8 V Noninverted, Inverted Differential Outputs powered by VCCO3 (Notes 1 and 2). 13, 12 Q5, Q5 CML Output 9, 17, GND Negative Supply Voltage, connected to Ground 24, 32 3 VREFAC0 Output Voltage Reference for CapacitorCoupled Inputs, only 7 VREFAC1 EP The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and must be electric- ally and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on INn/INn input, then, the device will be susceptible to self oscillation. Qn/Qn outputs have internal 50 source termination resistors. 2. All V , VCC0x and GND pins must be externally connected to a power supply for proper operation. CC