NBSG16M 2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer NBSG16M V V V V CC BB EE EE Exposed Pad (EP) 16 15 14 13 VTD 1 12 V CC D 2 11 Q NBSG16M D Q 3 10 VTD V 4 9 CC 56 7 8 V NC V V CC EE EE Figure 1. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 V Internal 50 Termination Pin. See Table 2. (Note 2) TD 2 D LVDS, CML, ECL, LVTTL, Inverted Differential Input (Note 2) LVCMOS Input 3 D LVDS, CML, ECL, LVTTL, Noninverted Differential Input. (Note 2) LVCMOS Input 4 V Internal 50 Termination Pin. See Table 2. (Note 2) TD 5 V Positive Supply Voltage. All V pins must be externally connected to Power Supply to CC CC guarantee proper operation. 6 NC No Connect 7 V Negative Supply Voltage. All V pins must be externally connected to Power Supply to EE EE guarantee proper operation. 8 V Negative Supply Voltage. All V pins must be externally connected to Power Supply to EE EE guarantee proper operation. 9 V Positive Supply Voltage. All V pins must be externally connected to Power Supply to CC CC guarantee proper operation. 10 Q CML Output Noninverted CML Differential Output with Internal 50 Source Termination Resistor. (Note 1) 11 Q CML Output Inverted CML Differential Output with Internal 50 Source Termination Resistor. (Note 1) 12 V Positive Supply Voltage. All V pins must be externally connected to Power Supply to CC CC guarantee proper operation. 13 V Negative Supply Voltage. All V pins must be externally connected to Power Supply to EE EE guarantee proper operation. 14 V Negative Supply Voltage. All V pins must be externally connected to Power Supply to EE EE guarantee proper operation. 15 V Internally Generated ECL Reference Output Voltage BB 16 V Positive Supply Voltage. All V pins must be externally connected to Power Supply to CC CC guarantee proper operation. EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat-sinking conduit. The pad is not electrically connected to the die but may be electrically and thermally connected to V on the PC board. EE 1. CML outputs require 50 receiver termination resistor to V for proper operation. CC 2. In the differential configuration when the input termination pin (V , V ) are connected to a common termination voltage, and if no signal TD TD is applied then the device will be susceptible to self-oscillation.