DATA SHEET www.onsemi.com LDO Regulator for RF and 1 Analog Circuits - Ultra-Low WLCSP4 WLCSP4 XDFN4 CASE 567JZ CASE 567KA CASE 711AJ Noise and High PSRR 250 mA MARKING DIAGRAMS NCP160 X X XX M A1 A1 The NCP160 is a linear regulator capable of supplying 250 mA 1 output current. Designed to meet the requirements of RF and analog circuits, the NCP160 device provides low noise, high PSRR, low X or XX = Specific Device Code quiescent current, and very good load/line transients. The device is M = Date Code designed to work with a 1 F input and a 1 F output ceramic capacitor. It is available in two thickness ultrasmall 0.35P, 0.64 mm x 0.64 mm Chip Scale Package (CSP) and XDFN 4 0.65P, 1 mm x PIN CONNECTIONS 1 mm. IN OUT Features Operating Input Voltage Range: 1.9 V to 5.5 V A2 A1 Available in Fixed Voltage Option: 1.8 V to 5.14 V 2% Accuracy Over Load/Temperature B1 B2 Ultra Low Quiescent Current Typ. 18 A Standby Current: Typ. 0.1 A EN GND Very Low Dropout: 80 mV at 250 mA (Top View) Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz Ultra Low Noise: 10 V RMS Stable with a 1 F Small Case Size Ceramic Capacitors Available in WLCSP4 0.64 mm x 0.64 mm x 0.4 mm WLCSP4 0.64 mm x 0.64 mm x 0.33 mm XDFN4 1 mm x 1 mm x 0.4 mm These Devices are PbFree and are RoHS Compliant (Top View) Typical Applications ORDERING INFORMATION Batterypowered Equipment See detailed ordering, marking and shipping information on Wireless LAN Devices page NO TAG of this data sheet. Smartphones, Tablets Cameras, DVRs, STB and Camcorders Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 18 NCP160/DNCP160 V V OUT IN IN OUT NCP160 C EN IN C OUT 1 F ON 1 F Ceramic Ceramic GND OFF Figure 1. Typical Application Schematics IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin CSP4 XDFN4 Name Description A1 4 IN Input voltage supply pin A2 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. B1 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN B2 2 GND Common ground connection EPAD EPAD Expose pad can be tied to ground plane for better power dissipation www.onsemi.com 2