Power Factor Controller, Interleaved, 2-Phase NCP1632 The NCP1632 integrates a dual MOSFET driver for interleaved PFC applications. Interleaving consists of paralleling two small stages in lieu of a bigger one, more difficult to design. This approach has several merits like the ease of implementation, the use of smaller www.onsemi.com components or a better distribution of the heating. MARKING DIAGRAM Also, Interleaving extends the power range of Critical Conduction Mode that is an efficient and costeffective technique (no need for low t diodes). In addition, the NCP1632 drivers are 180 phase rr NCP1632G SOIC16 shifted for a significantly reduced current ripple. AWLYWW D SUFFIX Housed in a SOIC16 package, the circuit incorporates all the CASE 751B features necessary for building robust and compact interleaved PFC A = Assembly Location stages, with a minimum of external components. WL = Wafer Lot Y = Year General Features WW = Work Week NearUnity Power Factor G = PbFree Package Substantial 180 Phase Shift in All Conditions Including Transient PIN ASSIGNMENT Phases ZCD2 ZCD1 Frequency Clamped Critical Conduction Mode (FCCrM) i.e., 1 FB REF5V/pfcOK Fixed Frequency, Discontinuous Conduction Mode Operation with Critical Conduction Achievable in Most Stressful Conditions Rt DRV1 FCCrM Operation Optimizes the PFC Stage Efficiency Over the OSC GND Load Range Vcc Vcontrol Outofphase Control for Low EMI and a Reduced rms Current in FFOLD DRV2 the Bulk Capacitor BO Latch Frequency Foldback at Low Power to Further Improve the Light OVP / UVP CS Load Efficiency (Top View) Accurate Zero Current Detection by Auxiliary Winding for Valley ORDERING INFORMATION Turn On Device Package Shipping Fast Line / Load Transient Compensation NCP1632DR2G SOIC16 2500 / Tape & Reel High Drive Capability: 500 mA / +800 mA (PbFree) Signal to Indicate that the PFC is Ready for Operation (pfcOK Pin) For information on tape and reel specifications, including part orientation and tape sizes, please V Range: from 10 V to 20 V CC refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Safety Features Output Over and Under Voltage Protection BrownOut Detection with a 500ms Delay to Help Meet Holdup Time Specifications SoftStart for Smooth Startup Operation Programmable Adjustment of the Maximum Power Over Current Limitation Detection of Inrush Currents Typical Applications Computer Power Supplies LCD / Plasma Flat Panels All Off Line Appliances Requiring Power Factor Correction Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: April, 2020 Rev. 7 NCP1632/DNCP1632 V V IN OUT D bypass R BO1 V L OUT V 2 AUX2 pfcOK R OUT1 R R L BO2 OVP1 V 1 AUX2 R ZCD2 R R ZCD1 OUT2 ZCD2 ZCD1 D 1 1 16 R OUT3 C pfcOK FB pfcOK R OVP2 2 15 R T DRV1 D Rt 2 3 14 M R 1 C OSC OVP FF OSC GND in 4 13 C OSC V C VCC CC Vcontrol M 5 12 2 C Ac line COMP2 RFOLD DRV2 R FFOLD BO3 R OVP3 6 11 R COMP1 BO Latch C 7 10 FOLD OVP/UVP CS EMI C COMP1 8 9 C Filter BO2 C C BULK IN R OVP OCP in R CS Figure 1. Typical Application Schematic Table 1. MAXIMUM RATINGS Symbol Rating Pin Value Unit V Maximum Power Supply Voltage Continuous 12 0.3, +20 V CC(MAX) V Maximum Input Voltage on Low Power Pins (Note 1) 1, 2, 3, 4, 6, 7, 0.3, +9.0 V MAX ) 8, 9, 10, 15, and 16 V V Pin Maximum Input Voltage 5 0.3, V (Note 2) V Control(MAX) Control Control(clamp) Power Dissipation and Thermal Characteristics P Maximum Power Dissipation T = 70C 550 mW D A R Thermal Resistance JunctiontoAir 145 C/W J A T Operating Junction Temperature Range 40 to +150 C J T Maximum Junction Temperature 150 C J(MAX) T Storage Temperature Range 65 to +150 C S(MAX) T Lead Temperature (Soldering, 10s) 300 C L(MAX) ESD Capability, HBM model (Note 3) 3 kV ESD Capability, Machine Model (Note 3) 200 V ESD Capability, Charged Device Model (Note 3) 1000 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. These maximum ratings (0.3 V / 9.0 V) guarantee that the internal ESD Zener diode is not turned on. More positive and negative voltages can be applied to the ZCD1 pin if the ESD Zener diode current is limited to 5 mA maximum. Typically, as detailed in the Zero Current Detection section, an external resistor is to be placed between the ZCD1 pin and its driving voltage to limit the ZCD1 source and sink currents to 5 mA or less. See Figure 2 and application note AND9654 for more details. The same is valid for the ZCD2 pin. 2. V is the pin5 clamp voltage. Control(clamp) 3. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22A114E Machine Model Method 200 V per JEDEC Standard JESD22A115A Charged Device Model Method 1000 V per JEDEC Standard JESD22C101E 4. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78. www.onsemi.com 2