DATA SHEET www.onsemi.com Linear Regulator - Dual-Rail, Very LowDropout, QFN20 DFN10 CASE 485DB CASE 485C Programmable SoftStart PIN CONNECTIONS 1.5 A NCP59748 The NCP59748 is dual rail very low dropout voltage regulator, 5 4 3 2 1 capable of providing an output current in excess of 1.5 A with a 6 20 IN OUT 7 19 IN OUT dropout voltage of 60 mV typ. at full load current. The devices are 8 18 IN GND OUT stable with ceramic and any other type of output capacitor 2.2 F. PG 9 17 NC This series contains adjustable output voltage version with output 10 16 BIAS FB voltage down to 0.8 V. Internal protection features consist of built-in 11 12 13 14 15 thermal shutdown and output current limiting protection. User-programmable Soft-Start and Power-Good pins are available on both QFN and DFN versions. QFN205 50.65P The NCP59748 is offered in DFN10 33 and QFN20 55 packages. 1 10 IN OUT Features 2 9 IN OUT Output Current in Excess of 1.5 A Thermal 3 8 PG FB V Range: 0.8 V to 5.5 V IN Pad BIAS 4 7 SS V Range: 2.7 V to 5.5 V BIAS 5 6 EN GND Output Voltage Range: 0.8 V to 3.6 V DFN103 30.5P Dropout Voltage: 60 mV at 1.5 A Programmable Soft-Start Open Drain Power Good Output MARKING DIAGRAMS Fast Transient Response 1 1 Stable with Any Type of Output Capacitor 2.2 F NCP NCP59748 Current Limit and Thermal Shutdown Protection 59748 AWLYYWW AYW These are PbFree Devices Applications QFN20 DFN10 Consumer and Industrial Equipment Point of Load Regulation A = Assembly Location FPGA, DSP and Logic Power Supplies WL = Wafer Lot YY, Y = Year Switching Power Supply Post Regulation WW, W = Work Week = Pb-Free Package NCP59748 (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information on page 4 of this data sheet. Figure 1. Typical Application Schematic Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: January, 2022 Rev. 4 NCP59748/D EN IN GND NC NC NC NC NC SS OUTNCP59748 Figure 2. Simplified Schematic Block Diagram Table 1. PIN FUNCTION DESCRIPTION Name QFN20 DFN10 Description IN 58 1, 2 Unregulated input to the device. EN 11 5 Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating. SS 15 7 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 200 s. BIAS 10 4 Bias input voltage for error amplifier, reference, and internal control circuits. PG 9 3 Power-Good (PG) is an open-drain, active-high output that indicates the status of V . When V exceeds the PG trip threshold, the PG pin goes into a OUT OUT high-impedance state. When V is below this threshold the pin is driven to a OUT low-impedance state. A pull-up resistor from 10 k to 1 M should be connected from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. FB 16 8 This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. OUT 1, 1820 9, 10 Regulated output voltage. A small capacitor (total typical capacitance 2.2 F, ceramic) is needed from this pin to ground to assure stability. NC 24, 13, 14, 17 N/A No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. GND 12 6 Ground PAD/TAB Should be soldered to the ground plane for increased thermal performance. www.onsemi.com 2