Linear Voltage Regulator 3 A for DDR1, DDR2, DDR3, LPDDR3, DDR4 V TT Termination NCP51200, NCV51200 www.onsemi.com The NCP/NCV51200 is a source/sink Double Data Rate (DDR) termination regulator specifically designed for low input voltage and lownoise systems where space is a key consideration. The NCP/NCV51200 maintains a fast transient response and only requires a minimum output capacitance of 20 F. The NCP/NCV51200 supports a remote sensing function and all power requirements for DFN10 DFNW10 DDR V bus termination. The NCP/NCV51200 can also be used in TT CASE 485C CASE 507AM low power chipsets and graphics processor cores that require dynamically adjustable output voltages. MARKING DIAGRAMS The NCP/NCV51200 is available in the thermallyefficient DFN10 Exposed Pad wettable flank package, and is rated both Green and 51200 Pbfree. XX ALYW Features For Automotive Applications XX = Specific Device Code Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails A = Assembly Location PV Voltage Range: 1.1 to 3.5 V CC L = Wafer Lot (Optional character ) Y = Year Integrated Power MOSFETs W = Work Week Fast LoadTransient Response = PbFree Package P Logic output pin to Monitor V Regulation GOOD TT (Note: Microdot may be in either location) EN Logic input pin for Shutdown mode V Reference Input Allows for Flexible Input Tracking Either RI Directly or Through Resistor Divider PIN CONNECTION Remote Sensing (V ) TTS + Builtin Soft Start, Under Voltage Lockout and Over Current Limit V 1 10 V RI CC Thermal Shutdown 2 9 PV P CC GOOD Small, LowProfile 10pin, 3x3 DFN Package V GND GND 3 8 TT NCV51200MWTXG (SFS), NCV51200MLTXG (SLP) Wettable 4 7 P EN GND Flank Options for Enhanced Optical Inspection V 5 6 V TTS RO NCV Prefix for Automotive and Other Applications Requiring Exposed Pad Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable* These Devices are PbFree and are RoHS Compliant ORDERING INFORMATION Applications See detailed ordering, marking and shipping information in the DDR Memory Termination package dimensions section on page 8 of this data sheet. Desktop PCs, Notebooks, and Workstations Servers and Networking equipment Telecom/Datacom, GSM Base Station Graphics Processor Core Supplies Set Top Boxes, LCDTV/PDPTV, Copier/Printers Chipset/RAM Supplies as Low as 0.5 V Active Bus Termination Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: June, 2021 Rev. 14 NCP51200/DNCP51200, NCV51200 PIN FUNCTION DESCRIPTION Pin Number Pin Name Pin Function 1 V V External Reference Input ( set to V / 2 thru resistor network ). RI TT DDQ 2 PV Power input. Internally connected to the output source MOSFET. CC 3 V Power Output of the Linear Regulator. TT 4 P Power Ground. Internally connected to the output sink MOSFET. GND 5 V V Sense Input. The V pin provides accurate remote feedback sensing of V . Connect V to the TTS TT TTS TT TTS remote DDR termination bypass capacitors. 6 V Independent Buffered V Reference Output. Sources and sinks over 5 mA. Connect to GND thru RO TT 0.1 F ceramic capacitor. 7 EN Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect to V for normal operation. DDQ 8 GND Common Ground. 9 P Power Good (Open Drain output). GOOD 10 V Analog power supply input. Connect to GND thru a 1 4.7 F ceramic capacitor. CC THERMAL Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple PAD vias for maximum power dissipation performance. ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit V , PV , V , V , V , V (Note 1) 0.3 to 6.0 V CC CC TT TTS RI RO EN, P (Note 1) 0.3 to 6.0 V GOOD P to GND (Note 1) 0.3 to +0.3 V GND Storage Temperature T 55 to 150 C STG Operating Junction Temperature Range T 150 C J ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following method: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Machine Model tested per AECQ100003 (EIA/JESD22A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. DISSIPATION RATINGS Derating Factor above Package T = 25 C Power Rating T = 25 C T = +85 C Power Rating A A A 10Pin DFN 1.92 W 19 mW/C 0.79 W THERMAL INFORMATION NCP51200 (*) DFN 3x3mm Symbol Thermal Metric 10 pins Unit R Junctiontoambient thermal resistance 53.9 C/W JA R Junctiontocase (top) thermal resistance 95.5 C/W JC(top) Junctiontoboard thermal resistance (1mm from package) 32.3 C/W R JB Junctiontotop thermal resistance 4.3 C/W JT Junctiontoboard thermal resistance (1mm from package) 32.3 C/W JB Junctiontocase (bot) thermal resistance 14.2 C/W R JC(bot) *1S2P JEDEC JESD517 PCB with 240 sqmm, 2 oz copper heat spreader. www.onsemi.com 2