NCV8165 LDO Regulator for RF and Analog Circuits - Ultra-Low Noise and High PSRR 500 mA www.onsemi.com The NCV8165 is a linear regulator capable of supplying 500 mA output current. Designed to meet the requirements of RF and analog circuits, the NCV8165 device provides low noise, high PSRR, low MARKING quiescent current, and very good load/line transients. The device is DIAGRAM designed to work with a 1 F input and a 1 F output ceramic capacitor. 1 It is available in DFNW8 3 mm x 3 mm package with wettable flanks. 8165L DFNW8, 3x3 330 Features CASE 507AD ALYW 1 Operating Input Voltage Range: 1.9 V to 5.5 V Available in Fixed Voltage Option: 1.8 V to 5.2 V A = Assembly Location L = Wafer Lot 2% Accuracy Over Load/Temperature Y = Year Ultra Low Quiescent Current Typ. 12 A W = Work Week Standby Current: Typ. 0.1 A = PbFree Package (Note: Microdot may be in either location) Very Low Dropout: 190 mV at 500 mA Ultra High PSRR: Typ. 85 dB at 20 mA, f = 1 kHz Ultra Low Noise: 8.5 V RMS PIN CONNECTIONS Stable with a 1 F Small Case Size Ceramic Capacitors Available in DFNW8 0.65P, 3 mm x 3 mm x 0.9 mm Package OUT 1 8 IN NCV Prefix for Automotive and Other Applications Requiring N/C 2 7 N/C Unique Site and Control Change Requirements AECQ100 EXP N/C36 N/C Qualified and PPAP Capable GND 4 5 EN These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant DFNW8 3x3 mm (Top View) Typical Applications Batterypowered Equipment Wireless LAN Devices ORDERING INFORMATION Smartphones, Tablets See detailed ordering and shipping information on page 9 of this data sheet. Cameras, DVRs, STB and Camcorders V V OUT IN IN OUT NCV8165 C EN IN C OUT 1 F ON 1 F Ceramic Ceramic GND OFF Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: September, 2019 Rev. 1 NCV8165/DNCV8165 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 8 IN Input voltage supply pin 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. 5 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN 4 GND Common ground connection EPAD EPAD Expose pad should be tied to ground plane for better power dissipation ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V 0.3 V to 6 V IN Output Voltage V 0.3 to V + 0.3, max. 6 V V OUT IN Chip Enable Input V 0.3 to V + 0.3, max. 6 V V CE IN Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AECQ100002 (EIA/JESD22A114) ESD Machine Model tested per AECQ100003 (EIA/JESD22A115) Latchup Current Maximum Rating tested per JEDEC standard: JESD78. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Unit Input Voltage V 1.9 5.5 V IN Junction Temperature T 40 125 C J Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2