N-Channel Logic Level Enhancement Mode Field Effect Transistor NDS331N General Description www.onsemi.com These NChannel logic level enhancement mode power field effect transistors are produced using ON Semiconductors proprietary, high cell density, DMOS technology. This very high density process is D especially tailored to minimize onstate resistance. These devices are particularly suited for low voltage applications in notebook G computers, portable phones, PCMCIA cards, and other battery S powered circuits where fast switching, and low inline power loss are SOT23/SUPERSOT23, 3 LEAD, 1.4x2.9 needed in a very small outline surface mount package. CASE 527AG Features 1.3 A, 20 V MARKING DIAGRAM R = 0.21 V = 2.7 V DS(on) GS Drain R = 0.16 V = 4.5 V DS(on) GS 3 Industry Standard Outline SOT23 Surface Mount Package Using 331M Proprietary SUPERSOT 3 Design for Superior Thermal and Electrical Capabilities 12 High Density Cell Design for Extremely Low R DS(on) Gate Source Exceptional OnResistance and Maximum DC Current Capability M = Date Code This is a PbFree Device D G S ORDERING INFORMATION Device Package Shipping NDS331N SOT233/ 3000 / SUPERSOT23 Tape & Reel (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: May, 2021 Rev. 7 NDS331N/DNDS331N ABSOLUTE MAXIMUM RATINGS T = 25C unless otherwise noted. A Symbol Parameter Ratings Unit V DrainSource Voltage 20 V DSS V GateSource Voltage Continuous 8 V GSS I Maximum Drain Current Continuous (Note 1a) 1.3 A D Maximum Drain Current Pulsed 10 P Maximum Power Dissipation (Note 1a) 0.5 W D Maximum Power Dissipation (Note 1b) 0.46 T , T Operating and Storage Temperature Range 55 to +150 C J STG Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL CHARACTERISTICS Symbol Parameter Ratings Unit R Thermal Resistance, JunctiontoAmbient (Note 1a) 250 C/W JA Thermal Resistance, JunctiontoCase (Note 1) 75 C/W R JC 1. R is the sum of the junctiontocase and casetoambient thermal resistance where the case thermal reference is defined as the solder JA mounting surface of the drain pins. R is guaranteed by design while R is determined by the users board design. JC CA T T T T J A J A 2 P (t) I (t) R D D DS(on) T J R (t) R R (t) JA JC CA Typical R using the board layouts shown below on 4.5x5 FR4 PCB in a still air environment: JA 2 2 a) 250C/W when mounted on a 0.02 in pad b) 270C/W when mounted on a 0.001 in pad of 2oz copper. of 2oz copper. Scale 1:1 on letter size paper www.onsemi.com 2