NLSX0102 2-Bit 20 Mb/s Dual-Supply Level Translator The NLSX0102 is a 2bit configurable dualsupply bidirectional auto sensing translator that does not require a directional control pin. The I/O V and I/O V ports are designed to track two different CC L www.onsemi.com power supply rails, V and V respectively. Both the V and V CC L CC L supply rails are configurable from 1.5 V to 5.5 V. This allows voltage MARKING logic signals on the V side to be translated into lower, higher or equal L DIAGRAM value voltage logic signals on the V side, and viceversa. CC A2 The NLSX0102 translator has integrated 10 k pullup resistors on AAG the I/O lines. The integrated pullup resistors are used to pullup the A1 AYWW I/O lines to either V or V . The NLSX0102 is an excellent match L CC 2 FLIPCHIP 8 D1 A1 for opendrain applications such as the I C communication bus. CASE 499BF Features V can be Less than, Greater than or Equal to V L CC AAG = Specific Device Code A = Assembly Location Wide V Operating Range: 1.5 V to 5.5 V CC Y = Year Wide V Operating Range: 1.5 V to 5.5 V L WW = Work Week HighSpeed with 24 Mb/s Guaranteed Date Rate Low BittoBit Skew PIN ASSIGNMENTS Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V A1 A2 I/O V 2 I/O V 1 CC CC Nonpreferential Powerup Sequencing Integrated 10 k Pullup Resistors GND B1 B2 V CC Small Space Saving Package 1.9 mm x 0.9 mm x 0.5 mm Flipchip8 C1 C2 V EN L This is a PbFree Device D1 D2 I/O V 2 I/O V 1 L L Typical Applications 2 I C, SMBus (Top View) Low Voltage ASIC Level Translation LOGIC DIAGRAM Mobile Phones, PDAs, Cameras V V GND L CC EN Important Information ESD Protection for All Pins Human Body Model (HBM) > 7000 V I/O V 1 I/O V 1 L CC I/O V 2 I/O V 2 L CC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Semiconductor Components Industries, LLC, 2011 1 Publication Order Number: July, 2018 Rev. 2 NLSX0102/DNLSX0102 V V L CC OneShot OneShot PU1 PU2 Block Block Gate R R Pullup Pullup Bias 10 k 10 k EN EN I/O V I/O V L CC N Figure 1. Block Diagram (1 I/O Line) PIN ASSIGNMENT FUNCTION TABLE Pins Description EN Operating Mode V V Supply Voltage L HiZ CC CC V V Supply Voltage H I/O Buses Connected L L GND Ground EN Output Enable, referenced to V L I/O V n I/O Port, referenced to V CC CC I/O V n I/O Port, referenced to V L L MAXIMUM RATINGS Symbol Parameter Value Condition Unit V Highside DC Supply Voltage 0.5 to +7.0 V CC V Lowside DC Supply Voltage 0.5 to +7.0 V L I/O V V referenced DC Input / Output Voltage 0.5 to +7.0 V CC CC I/O V V referenced DC Input / Output Voltage 0.5 to +7.0 V L L V Enable Control Pin DC Input Voltage 0.5 to +7.0 V EN I ShortCircuit Duration (I/O V and I/O V to GND) 50 Continuous mA I/O SC L CC I Input / Output Clamping Current (I/O V and I/O V ) 50 V < 0 mA I/OK L CC I/O T Storage Temperature 65 to +150 C STG Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2