ASM5P2305A, ASM5P2309A
3.3 V Zero Delay Buffer
Description
ASM5P2309A is a versatile, 3.3 V zero delay buffer designed to
distribute highspeed clocks. It accepts one reference input and drives
out nine lowskew clocks. It is available in a 16pin package. The
ASM5P2305A is the eightpin version of the ASM5P2309A. It
ASM5P2305A, ASM5P2309A
PLL CLKOUT
MUX
REF CLKA1
CLKA2
ASM5P2309A
PLL CLKOUT
CLKA3
REF
CLKA4
CLK1
CLKB1
S2 Select
ASM5P2305A
CLK2
Input
CLKB2
S1
Decoding
CLK3
CLKB3
CLK4
CLKB4
Figure 1. Block Diagram
Table 1. SELECT INPUT DECODING FOR ASM5P2309A
S2 S1 Clock A1 A4 Clock B1 B4 CLKOUT (Note 1) Output Source PLL ShutDown
0 0 Three state Three state Driven PLL N
0 1 Driven Three state Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and the output.
Zero Delay and Skew Control
For applications requiring zero inputoutput delay, all
All outputs should be uniformly loaded to achieve Zero
outputs, including CLKOUT, must be equally loaded. Even
Delay between input and output. Since the CLKOUT pin is
if CLKOUT is not used, it must have a capacitive load equal
the internal feedback to the PLL, its relative loading can
to that on other outputs, for obtaining zero inputoutput
adjust the inputoutput delay.
delay.
1500
1000
500
0
5
10 15 20 25 30
30 25 20 15 10 5 0
500
1000
1500
Figure 2. Output Load Difference: CLKOUT Load CLKA/CLKB Load (pF)