AN30183A 600mA Synchronous DC-DC Step Down Regulator (1ch) 300mA LDO Regulator (4ch) Multi Power Supply (High Efficiency Power LSI) FEATURES DESCRIPTION z High-Speed Response DC-DC Step Down Regulator AN30183A is a multi power supply LSI which has High- Circuit that employs Hysteretic System Speed Response DC-DC Step Down Regulators (1-ch) z DC-DC Step Down Regulator : 1-ch and LDO Regulators (4-ch). Input voltage Range VBAT :2.5V to 5.5V By this DC-DC system, when load current charges DVDD : 1.7V to 3.0V suddenly, it responds at high speed and minimizes the Output voltage Range 0.8 V to 2.4 V changes of output voltage. Up to 600 mA Output Current Since it is possible to use capacitors with small capacitance and it is unnecessary to add external parts z LDO Regulator : 4-ch for system phase compensation, this IC realizes Input voltage Range VBAT :2.5V to 5.5V downsizing of set and reducing in the number of external DVDD : 1.7V to 3.0V Output voltage Range 1.0 V to 3.3 V parts. 2 Up to 300 mA Output Current The output DC of each power supply is variable by I C control. 2 z I C control (2-slave address selectable) z 20 pin Wafer Level Chip Size Package (WLCSP) (Size : 1.56 mm 2.06 mm, 0.4 mm Pitch) APPLICATIONS Mobile phone, Portable appliance, etc SIMPLIFIED APPLICATION EFFICIENCY CURVE DDVBAT1 DVDD VB VIN2 4.7F AN30183A DCDC1 Efficiency 0.1F 4.7F4.7F 100 SDA 90 SCL DCDCOUT1 LX1 1H ASEL 80 FB1 4.7F DDGND1 70 REGCNT 60 50 AN30183A VLDO3 VLDO1 Vout=0.8V 1F 1F 40 Vout=1.2V 30 Vout=1.8V VLDO4 VLDO2 1F 1F Vout=2.4V 20 10 VREG REF RESETLDO1ON AGND 0 1F 1F 1 10 100 1000 Load Current mA Notes) This application circuit is an example. The operation of mass production set is not guaranteed. You should Condition ) perform enough evaluation and verification on the DDVBAT1 = DDVBAT2 = VB = VIN2 = 3.7V design of mass production set. You are fully responsible for the incorporation of the above Lo = 1.0 H, Cout = 4.7 F application circuit and information in the design of your equipment. Ver. AEB Publication date: October 2012 1 Efficiency % AN30183A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Notes VB,VIN2,DDVBAT1 6.0 V *1 Supply voltage DVDD 3.6 V *1 Output Current I A *1 IN Operating free-air temperature T 30 to + 85 C *2 opr Operating junction temperature T 30 to + 150 C *2 j Storage temperature T 55 to + 150 C *2 stg RESET,LDO1ON,FB1, *1 0.3 to V + 0.3 V VBAT REGCNT *3 Input Voltage Range *1 SCL,SDA,ASEL 0.3 to DVDD + 0.3 V *3 LX1,VREG,REF,SDA *1 Output Voltage Range 0.3 to V + 0.3 V VBAT LDO1,LDO2,LDO3,LDO4 *3 ESD HBM (Human Body Model) 2 kV Notes) Do not apply external currents and voltages to any pin not specifically mentioned. This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1:The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2:Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25 C. *3:V is voltage for DDVBAT1 = VB = VIN2, (V + 0.3) V must not be exceeded 6 V. VBAT VBA V is voltage for DVDD, (V + 0.3) V must not be exceeded 3.6 V. DVDD DVDD POWER DISSIPATION RATING PACKAGE PD ( Ta = 25 C) PD ( Ta = 85 C) Notes JA 20 pin Wafer level chip size Package 359.0 C / W 0.348 W 0.181 W *1 (WLCSP Type) Note). For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. *1:Glass Epoxy Substrate ( 4 Layers ) Glass-Epoxy: 50 X 50 X 0.8 t ( mm ) Die Pad Exposed , Soldered. CAUTION Although this has limited built-in ESD protection circuit, but permanent damage may occur on it. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the MOS gates Ver. AEB 2