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LPC11C12/C14
32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB
SRAM; C_CAN
Rev. 00.05 23 April 2010 Preliminary data sheet
1. General description
The LPC11C12/C14 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed
for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC11C12/C14 operate at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC11C12/C14 includes 16/32 kB of flash memory,
2
8 kB of data memory, one C_CAN controller, one Fast-mode Plus I C-bus interface, one
RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose
counter/timers, a 10-bit ADC, and 40 general purpose I/O pins.
On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included.
2. Features and benefits
System:
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
Serial Wire Debug.
System tick timer.
Memory:
32 kB (LPC11C14) or 16 kB (LPC11C12) on-chip flash programming memory.
8 kB SRAM.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
Flash ISP commands can be issued via UART or C_CAN.
Digital peripherals:
40 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
GPIO pins can be used as edge and level sensitive interrupt sources.
High-current output driver (20 mA) on one pin.
2
High-current sink drivers (20 mA) on two I C-bus pins in Fast-mode Plus.
Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
Programmable WatchDog Timer (WDT).
Analog peripherals:
10-bit ADC with input multiplexing among 8 pins.DRAFT
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LPC11C12/C14
NXP Semiconductors
Serial interfaces:
UART with fractional baud rate generation, internal FIFO, and RS-485 support.
Two SPI controllers with SSP features and with FIFO and multi-protocol
capabilities.
2 2
I C-bus interface supporting full I C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
C_CAN controller. On-chip C_CAN drivers included.
Clock generation:
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the system oscillator or the internal RC
oscillator.
Clock output function with divider that can reflect the system oscillator, IRC, CPU
clock, or the Watchdog clock.
Power control:
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Processor wake-up from Deep-sleep mode via a dedicated start logic using 13 of
the GPIO pins.
Power-On Reset (POR).
Brownout detect with four separate thresholds for interrupt and forced reset.
Unique device serial number for identification.
Single 3.3 V power supply (1.8 V to 3.6 V).
Available as 48-pin LQFP package.
3. Applications
eMetering Industrial and sensor based networks
Elevator systems White goods
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC11C12FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 sot313-2
1.4 mm
LPC11C14FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 7 sot313-2
1.4 mm
LPC11C12_C14_0 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved.
Preliminary data sheet Rev. 00.05 23 April 2010 2 of 49