PE42722
Document Category: Product Specification
UltraCMOS SPDT RF Switch, 51794 MHz
Features
Figure 1 PE42722 Functional Diagram
Supports DOCSIS 3.0/1 requirements
Exceptional harmonics performance
RFC
2fo of 117 dBc @ 170 MHz
3fo of 134 dBc @ 170 MHz
Best in class linearity across frequency band
Low insertion loss and high isolation performance
RF1 RF2
Insertion loss of 0.3 dB @ 1218 MHz
Isolation of 50 dB @ 204 MHz
High ESD performance of 1.5 kV HBM
CMOS Control Driver
Packaging 32-lead 5 5 mm QFN
V1
Applications
Broadband market (DOCSIS 3.0/1)
Cable modem
Set-top box
Filter bank switching
Relay replacement to switch between DOCSIS 3.0
and DOCSIS 3.1 configurations
Product Description
The PE42722 is a HaRP technology-enhanced reflective SPDT RF switch designed for use in cable applica-
tions including DOCSIS 3.0/1 cable modem and set-top box. It delivers high linearity and excellent harmonics
performance in the 51794 MHz band. It also features low insertion loss and high isolation performance that
makes the PE42722 ideal for DOCSIS 3.1 applications.
The PE42722 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator
(SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of
conventional CMOS.
20142016, Peregrine Semiconductor Corporation. All rights reserved. Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-60151-3 (06/16)
www.psemi.comPE42722
SPDT RF Switch
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 Absolute Maximum Ratings for PE42722
Parameter/Condition Min Max Unit
Supply voltage, V
0.3 5.5 V
DD
Digital input voltage, V1 0.3 3.6 V
(1)
87.5 dBmV
Maximum input power
Maximum junction temperature +150 C
Storage temperature range 65 +150 C
(2)
1500 V
ESD voltage HBM, all pins
(3)
200 V
ESD voltage MM, all pins
(4)
250 V
ESD voltage CDM, all pins
Notes:
1) 100% duty cycle, all bands, 75 .
2) Human body model (MIL-STD 883 Method 3015).
3) Machine model (JEDEC JESD22-A115).
4) Charged device model (JEDEC JESD22-C101).
Page 2 DOC-60151-3 (06/16)
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