PE43704B-Z

Product Specification PE43704 UltraCMOS RF Digital Step Attenuator, 7-bit, 31.75 dB with Optional Vss Bypass Mode EXT Product Description 9 kHz - 8 GHz The PE43704 is a HaRP technology-enhanced, high linearity, 7-bit 50 RF digital step attenuator (DSA). It Features offers maximum power handling of 28 dBm up to 8 GHz HaRP technology enhanced and covers a 31.75 dB attenuation range in 0.25 dB, Safe attenuation state transitions 0.5 dB, or 1.0 dB steps. The PE43704 is a pin-compatible version of PE43703. It provides multiple CMOS control Attenuation options: covers a 31.75 dB interfaces and an optional Vss bypass mode to improve range in 0.25 dB, 0.5 dB, or 1.0 dB steps EXT spurious performance. It maintains high attenuation 0.25 dB monotonicity for 6 GHz accuracy over frequency and temperature and exhibits 0.50 dB monotonicity for 7 GHz very low insertion loss and low power consumption. No 1.00 dB monotonicity for 8 GHz blocking capacitors are required if DC voltage is not High power handling 8 GHz in 50 present on the RF ports. 28 dBm CW The PE43704 is manufactured on pSemis UltraCMOS 31 dBm instantaneous power process, a patented variation of silicon-on-insulator (SOI) High linearity technology on a sapphire substrate, offering the IIP3 of 61 dBm performance of GaAs with the economy and integration of conventional CMOS. 1.8V/3.3V control logic Programming modes Figure 1. Package Type Direct parallel 32-lead 5x5 QFN Latched parallel Serial Serial Addressable High-attenuation state power-up (PUP) ESD performance 1.5kV HBM on all pins Figure 2. Functional Diagram DOC-02161 Document No. DOC-16514-9 www.psemi.com 20122020 pSemi Corp. All rights reserved. Page 1 of 21 PE43704 Product Specification Table 1. Electrical Specifications: 0.25 dB steps +25C, V = 2.3V to 5.5V, Vss = 0V or DD EXT V = 3.4V to 5.5V, Vss = -3.4V (Z = Z = 50 ) unless otherwise noted DD EXT S L Parameter Condition Frequency Min Typ Max Unit Operating frequency 9 kHz 6000 MHz As shown Attenuation range 0.25 dB Step 0 31.75 dB 9 kHz 2 GHz 1.3 1.6 dB Insertion loss 2 GHz 4 GHz 1.7 2.0 dB 4 GHz 6 GHz 2.4 2.8 dB + (0.15 + 4.5% of dB Attenuation Setting) 9 KHz 4 GHz - (0.1 + 2% of dB Attenuation Setting) 0 dB 15.75 dB Attenuation settings + (0.15 + 6% of dB Attenuation Setting) 4 GHz 6 GHz - (0.15+1% of dB Attenuation Setting) Attenuation error + (0.15 + 4.5% of dB Attenuation Setting) 9 KHz 4 GHz - (0.1 + 2.5% of dB Attenuation Setting) 16 dB 31.75 dB Attenuation settings + (0.25 + 6.5% of dB Attenuation Setting) 4 GHz 6 GHz - (0.2+1% of dB Attenuation Setting) 9 kHz 4 GHz 20 dB Return loss Input port 4 GHz 6 GHz 15 dB 9 kHz 4 GHz 17 dB Return loss Output port 4 GHz 6 GHz 13 dB Relative phase 0 dB 31.75 dB Attenuation settings 9 kHz 6 GHz 58 deg 1 Input 1dB compression point 50 MHz 6 GHz 32 34 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 50 MHz 6 GHz 61 dBm 2 Typical spurious value Vss = 0V 140 dBm EXT RF Trise/Tfall 10% / 90% RF 600 ns Settling time RF settled to within 0.05 dB of final value 2 s Switching time 50% CTRL to 90% or 10% RF 1.1 s Notes: 1. The input 1dB compression point is a linearity figure of merit. Refer to Table 5 for the RF input power P (50) IN 2. To prevent negative voltage generator spurs, supply 3.4 volts to VssEXT 20122020 pSemi Corp. All rights reserved. Document No. DOC-16514-9 UltraCMOS RFIC Solutions Page 2 of 21