Product Information

QPL9503SR

QPL9503SR electronic component of Qorvo

Datasheet
RF Amplifier 1-6GHz Gain 21.6dB NF .9dB OIP3 35dBm

Manufacturer: Qorvo
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

100: USD 3.5694 ea
Line Total: USD 356.94

0 - Global Stock
MOQ: 100  Multiples: 100
Pack Size: 100
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 10 May to Tue. 14 May

MOQ : 100
Multiples : 100

Stock Image

QPL9503SR
Qorvo

100 : USD 3.7296
200 : USD 3.1864
500 : USD 3.1621

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Mounting Style
Package / Case
Type
Operating Frequency
P1dB - Compression Point
Gain
Operating Supply Voltage
NF - Noise Figure
OIP3 - Third Order Intercept
Minimum Operating Temperature
Maximum Operating Temperature
Operating Supply Current
Packaging
Series
Test Frequency
Brand
Number Of Channels
Development Kit
Input Return Loss
Product Type
Factory Pack Quantity :
Subcategory
Cnhts
Hts Code
Mxhts
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QPL9503 Ultra Low-Noise, Flat Gain LNA General Description The QPL9503 is a flat-gain, high-linearity, ultra-low noise amplifier in a small 2 x 2 mm surface-mount package. The LNA provides a gain flatness of 2 dB (peak-to-peak) over a wide bandwidth from 3 to 6 GHz. At 5.5 GHz, the amplifier typically provides 21.6 dB gain, +35.5 dBm OIP3 at a 56mA bias setting, and 0.95 dB noise figure. The LNA can be 8 Pin 2X2 mm DFN Package biased from a single positive supply ranging from 3.3 to 5 volts. The device is housed in a green/RoHS-compliant Product Features industry-standard 2x2 mm package. 0.6-6 GHz Operational Bandwidth The QPL9503 is internally matched using a high Ultra low noise figure, 0.95 dB NF 5.5 GHz performance E-pHEMT process and only requires five Bias adjustable for linearity optimization external components for operation from a single positive 35.5 dBm OIP3 at 65mA IDD supply: an external RF choke and blocking/bypass Shut-down mode pin with 1.8V TTL logic capacitors and a bias resistor going to pin 1. This LNA integrates a shut-down biasing capability to allow for Unconditionally stable operation in TDD applications. Integrated shutdown control pin Maintains OFF state with high Pin drive The QPL9503 is optimized for linear performance across +3V to +5V supply does not require -Vgg the 3 to 6 GHz frequency band but can operate down to 600 MHz. Functional Block Diagram Applications 4.5G, 5G Massive MIMO Pin 1 Reference Mark Repeaters / DAS Mobile Infrastructure 1 8 Vbias NC LTE-U / LAA 2 7 RF In RF Out L-band, S-band, C-band radios 3 6 General Purpose Wireless NC GND TDD or FDD systems 4 5 GND Shut Down Backside Paddle - RF/DC GND Ordering Information Top View Part No. Description QPL9503SR 100 pcs on 7 reel QPL9503TR7 2500 pcs on 7 reel QPL9503EVB-01 5-6GHz Tuned Evaluation Board Standard T/R size = 2500 pieces on a 7 reel Data Sheet, Rev E, June 10, 2020 Subject to change without notice 1 of 9 www.qorvo.com QPL9503 Ultra Low-Noise, Flat Gain LNA Absolute Maximum Ratings Recommended Operating Conditions Parameter Rating Parameter Min Typ Max Units Storage Temperature 65 to 150C Supply Voltage (VDD) 3.3 5.0 5.25 V Supply Voltage (V ) +7 V T 40 +105 C DD CASE 6 RF Input Power, CW, 50, T=25C +30 dBm Tj for >10 hours MTTF +190 C RF Input Power, WCDMA, 10dB PAR +27 dBm Electrical specifications are measured at specified test RF Input Power, CW, OFF State +30 dBm conditions. Specifications are not guaranteed over all recommended operating conditions. Operation of this device outside the parameter ranges given above may cause permanent damage. Electrical Specifications Test conditions unless otherwise noted: VDD =+5V, Temp=+25C, 50 system. Parameter Conditions Min Typ Max Units Operational Frequency Range 600 6000 MHz Test Frequency 5500 MHz Gain 18.5 21.6 22.5 dB Input Return Loss 10 dB Output Return Loss 9 dB (1) Noise Figure 0.9 1.3 dB Output P1dB +19 dBm Output IP3 Pout=+2 dBm/tone, f=1 MHz +30 +35.5 dBm On state 0 0.63 V Power Shutdown Control (pin 5) Off state (Power down) 1.17 VDD V On state 35 56 90 mA Current, I DD Off state (Power down) 3 mA Shutdown pin current, I V 1.17 V 140 A SD PD LNA ON to OFF 20 ns Switching Speed LNA OFF to ON 400 ns Thermal Resistance, channel to case 48 C/W jc Note: 1) Noise figure data has input trace loss de-embedded. Data Sheet, Rev E, June 10, 2020 Subject to change without notice 2 of 9 www.qorvo.com

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits:
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