2305NZT-1DCG Renesas

IDT2305NZT 2.5V CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE 2.5V CLOCK BUFFER IDT2305NZT FEATURES: DESCRIPTION: Clock Distribution The IDT2305NZT is a high-speed clock buffer, designed to address 10MHz to 133MHz operating frequency high-speed clock distribution applications. IDT2305NZT accepts one Distributes one clock input to one bank of five outputs reference input, and drives out five low skew clocks. Output Skew < 250ps No external RC network required Operates at 2.5V VDD Available in SOIC package Available in commercial and industrial temperature range FUNCTIONAL BLOCK DIAGRAM 8 CLKOUT 3 CLK1 1 Control REF Logic 2 CLK2 5 CLK3 7 CLK4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2012 1 DSC 7020/4IDT2305NZT 2.5V CLOCK BUFFER COMMERCIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating Max. Unit VDD Supply Voltage Range 0.5 to +4.6 V (2) VI Input Voltage Range (REF) 0.5 to +5.5 V REF 1 8 CLKOUT VI Input Voltage Range 0.5 to V CLK2 CLK4 2 7 (except REF) VDD+0.5 IIK (VI < 0) Input Clamp Current 50 mA VDD 3 6 CLK1 IO (VO = 0 to VDD) Continuous Output Current 50 mA GND 4 5 CLK3 VDD or GND Continuous Current 100 mA TA = 55C Maximum Power Dissipation 0.7 W (3) (in still air) TSTG Storage Temperature Range 65 to +150 C SOIC Operating Industrial Temperature -40 to +85 C TOP VIEW Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. APPLICATIONS: SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number Type Functional Description (1) REF 1 IN Input reference clock, 3.3V tolerant input (2) CLK2 2 OUT Output clock (2) CLK1 3 OUT Output clock GND 4 GND Ground (2) CLK3 5 OUT Output clock VDD 6 PWR 2.5V Supply (2) CLK4 7 OUT Output clock (2) CLKOUT 8 OUT Output clock NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 2