557G-06LF

DATASHEET 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX ICS557-06 Description Features The ICS557-06 is a two to four differential clock mux Packaged in 20-pin TSSOP designed for use in PCI-Express applications. The device Pb (lead) free packaging selects one of the two differential HCSL input pairs and fans Operating voltage of 3.3 V out to four pairs of differential HCSL or LVDS outputs. Low power consumption Input differential clock of up to 200 MHz Jitter 60 ps (cycle-to-cycle) Output-to-output skew of 50 ps Available in industrial temperature range (-40 to +85C) For PCIe Gen2/3 applications, see the 5V41067A Block Diagram OE VDD 2 CLKA CLKA IN1 CLKB IN1 CLKB MUX IN2 2 to 1 CLKC CLKC IN2 CLKD CLKD 2 Rr (IREF) SEL GND PD IDT 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 1 ICS557-06 REV M 070512ICS557-06 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX PCIE FAN OUT BUFFER Pin Assignment Select Table SEL 1 20 CLKA SEL Input Pair VDDIN 2 19 CLKA selected IN1 3 18 CLKB 0IN2/ IN2 IN1 4 17 CLKB 1IN1/ IN1 PD 5 16 GND IN2 6 15 VDD 7 14 CLKC IN2 OE 8 13 CLKC 9 12 CLKD GND 10 11 IREF CLKD 20-pin (173 mil) TSSOP Pin Descriptions Pin Pin Pin Pin Description Name Type 1 SEL Input SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. 2 VDDIN Power Connect to +3.3 V. Supply voltage for Input clocks. 3 IN1 Input HCSL true input signal 1. 4 IN1 Input HCSL complimentary input signal 1. 5 PD Input Powers down the chip and tri-states outputs when low. Internal pull-up 6 IN2 Input HCSL true input signal 2. 7 IN2 Input HCSL complimentary input signal 2. 8 OE Input Provides fast output on, tri-states output (High = enable outputs Low = disable). Internal pull-up resistor outputs. 9 GND Power Connect to ground. 10 Rr(IREF) Output Precision resistor attached to this pin is connected to the internal current 11 CLKD Output Differential Complimentary output clock D. 12 CLKD Output Differential True output clock D. 13 CLKC Output Differential Complimentary output clock C. 14 CLKC Output Differential True output clock C. 15 VDDOUT Power Connect to +3.3 V. Supply Voltage for Output Clocks. 16 GND Power Connect to ground. 17 CLKB Output Differential Complimentary output clock B. 18 CLKB Output Differential True output clock B. 19 CLKA Output Differential Complimentary output clock A. 20 CLKA Output Differential True output clock A. IDT 2 TO 4 DIFFERENTIAL PCIE GEN1 CLOCK MUX 2 ICS557-06 REV M 070512